Overview
ImperasTS-ISA is part of the ImperasTS family of directed test suites for RISC-V verification. It is described as providing architectural validation tests that are similar to compliance suites.[1]
Packaging and relationship to ImperasDV
ImperasTS-ISA is included with ImperasDV licences.[2]
Role in verification flows
Within the cited RISC-V verification discussion, the ImperasTS family is presented as a set of directed suites that complements constrained-random stimulus by targeting areas where random stimulus can leave coverage gaps.[3] ImperasTS-ISA specifically addresses architectural validation, while other ImperasTS family members address vector, virtual-memory, and protection-oriented scenarios.[4]
[1]: ImperasTS-ISA is described as architectural validation tests similar to compliance suites. [2]: ImperasTS-ISA is stated to be included with ImperasDV licences. [3]: The ImperasTS directed suites are described as efficiently targeting areas where random stimulus often leaves gaps. [4]: The cited ImperasTS family list includes TS-ISA, TS-VECT, and TS-MMU/PMP/ePMP suites.