BlackParrot Core

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BlackParrot Core is a processor core used as a target in the ProcessorFuzz evaluation. The provided evidence reports several BlackParrot bugs involving RISC-V ISA-visible behavior, including floating-point/CSR issues and an x0 zero-register pipeline bypass issue, and notes that DIFUZZRTL instrumentation of BlackParrot failed because of limited SystemVerilog-to-FIRRTL conversion support.

First seen 5/28/2026

Last seen 5/29/2026

Evidence 6 chunks

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Overview

BlackParrot Core is a processor core evaluated in the ProcessorFuzz study. In the provided evidence, BlackParrot appears as a target for processor fuzzing and as the core associated with multiple discovered bugs involving RISC-V architectural behavior, floating-point state, and control and status registers (CSRs).

The ProcessorFuzz paper also reports an evaluation limitation for BlackParrot: DIFUZZRTL instrumentation failed for BlackParrot because of limited support for SystemVerilog-to-FIRRTL conversion. As a result, the study used DIFUZZRTL as a comparison point but could not instrument BlackParrot in the same way as designs supported by that conversion flow.

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RELATIONSHIPS

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ProcessorFuzz ← evaluates 100% 2e

ProcessorFuzz was evaluated using the BlackParrot Core processor.

RISC-V ISA implements → 100% 1e

BlackParrot Core is an open-source RISC-V core implementing the RISC-V ISA.

SystemVerilog HDL implements → 100% 1e

BlackParrot Core is designed in SystemVerilog HDL.

LINKED ENTITIES

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ProcessorFuzz EVALUATES Extracted graph relationship

RISC-V ISA IMPLEMENTS Extracted graph relationship

SystemVerilog HDL IMPLEMENTS Extracted graph relationship

CITATIONS

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6 citations — click to expand

[1] BlackParrot was a processor core evaluated in the ProcessorFuzz study, and the provided evidence reports multiple BlackParrot bugs. ProcessorFuzz: Processor Fuzzing with Control and

[2] The evidence lists BlackParrot Bugs 1-3: non-boxed single-precision floating-point values not interpreted as NaNs, read-after-write dependencies on fcsr.fflags not satisfied, and mstatus.FS unexpectedly updated when fcsr is written while FS is not set, with statuses Confirmed #971, Fixed #994, and Fixed #969. ProcessorFuzz: Processor Fuzzing with Control and

[3] Bug 6 concerns BlackParrot reading x0 as non-zero when a preceding division instruction writing to x0 is still in the pipeline, due to bypassing the division result even when the destination register is x0. ProcessorFuzz: Processor Fuzzing with Control and

[4] ProcessorFuzz exposed the x0 issue because the test input caused an fflags CSR transition due to division by zero, and the paper describes a possible malware-obfuscation consequence involving jumps computed using x0. ProcessorFuzz: Processor Fuzzing with Control and

[5] DIFUZZRTL instrumentation of BlackParrot failed because of limited support for SystemVerilog-to-FIRRTL conversion. ProcessorFuzz: Processor Fuzzing with Control and

[6] The ProcessorFuzz evaluation used time-to-exposure as the elapsed time from the start of fuzzing until a bug is exposed and ran fuzzing instances with a 48-hour limit. ProcessorFuzz: Processor Fuzzing with Control and