Recurrent Neural Network-Based Constraint Alteration for PRG

Recurrent Neural Network-Based Constraint Alteration for PRG is a simulation-based processor verification technique in which a recurrent neural network (RNN) dynamically changes the constraints of a pseudorandom generator (PRG) using coverage feedback from simulation. The approach was proposed for improving coverage closure in processor verification and for identifying a compact set of high-coverage stimuli suitable for regression testing.^[1]

Overview

In simulation-based processor verification, a common workflow is to generate input stimuli using pseudorandom generators, apply those stimuli to the processor under verification, and monitor functional coverage to estimate verification completeness.^[1] Stimuli may be represented in different forms, including bit vectors applied to processor input ports or programs loaded directly into program memory.^[1]

The RNN-based constraint alteration technique modifies the PRG constraints dynamically rather than relying on a fixed random-generation configuration. The RNN receives feedback from the simulation coverage state of the design under verification and uses that information to guide subsequent stimulus generation.^[1]

Motivation

Processor verification often requires reaching a broad functional coverage space. In PRG-based verification, random or constrained-random stimuli may fail to efficiently reach uncovered functionality, especially when the coverage state space is large. The cited work addresses this by closing the loop between simulation coverage feedback and stimulus generation constraints.^[1]

The core motivation is to accelerate coverage closure, meaning the point at which the verification process has exercised the intended functional coverage targets sufficiently to determine verification completeness.^[1]

Method

The technique can be summarized as a feedback-driven verification loop:

A pseudorandom generator creates processor stimuli under a set of constraints.^[1]
The generated stimuli are applied to the processor design under verification.^[1]
Simulation monitors functional coverage achieved by those stimuli.^[1]
Coverage feedback is provided to a recurrent neural network.^[1]
The RNN dynamically alters the PRG constraints to influence future stimulus generation.^[1]

The use of an RNN is significant because the verification process is sequential: each round of generated stimuli changes the observed coverage state, and future constraint choices can depend on prior coverage history.

Stimulus Types

The approach is applicable to multiple stimulus representations used in processor verification. The cited work specifically notes two examples:

Bit-vector stimuli, applied directly to processor input ports.^[1]
Program-based stimuli, loaded directly into program memory.^[1]

This makes the method relevant both to low-level input-port testing and to instruction/program-level verification flows.

Demonstration Platform

For demonstration, the authors used processors provided by Codasip. The stated reason was that their coverage state space was reasonably large and varied across different processor types.^[1]

Although the experiments used Codasip processors, the authors state that the presented techniques are widely applicable.^[1]

Reported Results

The reported experimental results indicate two main benefits:

Faster coverage closure: coverage closure was achieved much sooner than with the baseline approach described in the paper.^[1]
Regression-test stimulus reduction: the method was able to isolate a small set of high-coverage stimuli that could be reused for regression testing.^[1]

These results suggest that RNN-guided PRG constraint adaptation can improve both verification efficiency and the construction of compact regression suites.

Publication Information

The work is associated with the paper Automation of Processor Verification Using Recurrent Neural Networks.^[1] It was presented at MTVCon 2017, contains 6 pages and 6 figures, and was listed on arXiv as arXiv:1803.09810 [cs.OH] with DOI 10.48550/arXiv.1803.09810.^[1]

References

^[1] Evidence excerpt for arXiv:1803.09810, Automation of Processor Verification Using Recurrent Neural Networks, describing dynamic PRG constraint alteration using recurrent neural networks for simulation-based processor verification.