Overview
Constraint Satisfaction Problem-based Test Generation is a processor-verification technique in which constraints are used as part of the test-input specification and are processed by Constraint Satisfaction Problem (CSP) or Satisfiability Modulo Theories (SMT) solvers to generate processor-level stimuli. The technique appears in the broader class of simulation-based processor verification approaches that rely on test generation. [C1]
Role in processor verification
In the cited survey context, CSP/SMT-based generation is described as one direction among model-based test generators. These generators use an input-format specification to guide stimulus generation; constraint-based variants encode specification requirements as constraints and solve them with CSP or SMT technology. [C1]
Multi-instruction constraints
The evidence also notes work on optimization techniques for propagating constraints among multiple instructions more effectively. This indicates that CSP/SMT-based processor test generation can involve dependencies that span instruction sequences rather than only isolated instructions. [C2]
Relationship to coverage-guided fuzzing
The paper Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing discusses CSP/SMT-based test generation as related work in processor verification, alongside other simulation-based stimulus-generation techniques. It contrasts these established test-generation directions with a fuzzing-based approach that generates instruction-sequence test cases, uses co-simulation, supports arbitrary control flows including self-loops, and applies domain-specific mutation procedures. [C3]