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Bayesian network-based coverage-directed test generation

Technique WIKI v1 · 6/25/2026

A functional verification technique that uses Bayesian networks to direct the generation of test stimuli toward hard-to-reach coverage targets, originally proposed for processor and hardware design validation and cited by later RISC-V verification work.

Overview

Bayesian network-based coverage-directed test generation is a functional verification technique that applies Bayesian networks to bias the random generation of test stimuli toward coverage points that are difficult to reach. In this approach, observed coverage feedback is used to update a Bayesian network model whose conditional probability distributions then steer subsequent test generation, so that unhit or rarely-hit coverage targets are explored more aggressively while already-covered targets are deprioritized [BRAUN-2004-EFFICIENCY-BN-CDTG].

Origin and evaluation

The technique is associated with the paper Enhancing the efficiency of Bayesian network based coverage directed test generation by M. Braun, S. Fine, and A. Ziv, presented at the Ninth IEEE International High-Level Design Validation and Test Workshop in Sonoma, USA, in 2004 [BRAUN-2004-EFFICIENCY-BN-CDTG]. The paper focuses on improving the efficiency of Bayesian-network-based coverage-directed test generation for hardware functional verification [BRAUN-2004-EFFICIENCY-BN-CDTG].

Relationship to other coverage-directed test-generation approaches

A 2022 paper on coverage-guided processor verification situates Bayesian network-based coverage-directed test generation among a broader family of coverage-guided test-generation (CGF) and machine-learning-based test-generation approaches, alongside symbolic-execution-based test generation at the ISS level and fuzzing-based processor-verification methods [BRUNS-2022-CGF]. In the same paper, it is contrasted with coverage-guided fuzzing approaches that do not require a bus-centric grammar because they robustly mutate binary instructions, and that do not include a method to check for errors in the design under test automatically [BRUNS-2022-CGF].

Context in processor verification

Bayesian network-based coverage-directed test generation has been used as a representative machine-learning-based coverage-directed technique in surveys of RISC-V processor verification, which list it alongside semi hand-written directed test suites, randomized instruction-pattern generation, constraint-based specification-driven generation, and coverage-guided fuzzing [BRUNS-2022-CGF]. Within this landscape, it is cited as one of the established approaches against which newer coverage-guided and formal methods are compared [BRUNS-2022-CGF].

Limitations

Coverage-directed approaches based on Bayesian networks have been noted to require manual effort and to depend on a model of the design under verification that is not needed by purely grammar-free fuzzing-based methods [BRUNS-2022-CGF]. They also do not by themselves provide automatic error-detection mechanisms for the design under test, in contrast to methods that compare ISS and RTL-core outputs [BRUNS-2022-CGF].

LINKED ENTITIES

1 links
Enhancing the efficiency of Bayesian network based coverage directed test generation EVALUATES

CITATIONS

4 sources
4 citations
[1] Bayesian network-based coverage-directed test generation uses Bayesian networks to bias random test stimulus generation toward hard-to-reach coverage targets, using observed coverage feedback to update the network's conditional probability distributions. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing
[2] The technique was introduced and its efficiency improved in the 2004 paper *Enhancing the efficiency of Bayesian network based coverage directed test generation* by Braun, Fine, and Ziv at the Ninth IEEE International High-Level Design Validation and Test Workshop in Sonoma, USA. A RISC-V Test Sequences Generation Method Based on Instruction ...
[3] Bayesian network-based coverage-directed test generation is cited as an established machine-learning-based coverage-directed test generation approach in surveys of RISC-V processor verification, alongside randomized instruction-pattern generation, constraint-based specification-driven generation, and coverage-guided fuzzing. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing
[4] Bayesian-network-based coverage-directed test generation has been noted to require manual modeling effort and does not by itself include automatic error-detection mechanisms for the design under test, unlike ISS/RTL co-simulation and coverage-guided fuzzing methods. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing