Overview

Application Compilation is a compilation technique tailored for architectures that pair a general-purpose processor with runtime reconfigurable cells implementing custom instructions as processor extensions. In this setting, the compiler must not only translate the application but also identify, select, and map the application's computational patterns onto the available extensions, while scheduling and binding operations efficiently.

The technique was articulated as a constraint programming (CP) formulation in the design framework IFPEC (Integrated Framework for Processor Extension Compilation), in which custom instructions and applications are both modeled as graphs and matched using subgraph isomorphism and connected-component constraints.

Approach

The CP-based application compilation flow operates on a graph representation of the application and a library of custom-instruction patterns. Its main steps are:

1. Pattern identification — Custom instructions (computational patterns) are expressed as graphs and matched against the application graph via subgraph isomorphism.
2. Connected-component constraints — Encode structural and connectivity requirements of the selected extensions within the application's dataflow graph.
3. Extension selection — Chooses which subset of candidate custom instructions should be realized on the reconfigurable fabric.
4. Application scheduling — Orders application operations, including those mapped to the extensions, on the combined processor + reconfigurable-cell architecture.
5. Binding and routing — Assigns operations to hardware resources and routes data through the interconnect between the host processor and the reconfigurable cells.

A key advantage of expressing the problem in CP is that heterogeneous constraints (architectural, timing, resource, and connectivity) can be combined into a single model, allowing extension selection, scheduling, and binding to be solved jointly and improving the quality of results compared with solving them sequentially.

Target Architecture

The technique assumes an architecture in which runtime reconfigurable cells implementing the selected extensions are tightly connected to a host processor. This coupling is central because compilation decisions (scheduling, binding, routing) all assume low-latency interaction between the processor and the reconfigurable fabric.

Framework: IFPEC

IFPEC is the integrated design framework that implements this application-compilation approach. Built using Constraint Programming, IFPEC unifies extension identification, selection, application scheduling, binding, and routing under a common constraint model, and has been used to validate the approach on representative experimental benchmarks.

Related Compilation Contexts

While the IFPEC formulation targets custom-instruction extension generation, other compilation contexts share the term "application compilation" in a broader sense:

• High-Level Synthesis (HLS) compilation of memory-bound applications for FPGAs can take minutes to days per bitstream because place-and-route dominates, even though RTL pipeline and memory organization are known within seconds; this early information is exploited to build fast performance models for HLS-generated designs.
• WebAssembly compilation of unmodified Unix applications has been shown to run on average 45% (Firefox) to 55% (Chrome) slower than native code on the SPEC CPU suite, reflecting the cost of compiling general-purpose applications to a sandboxed, browser-hosted runtime.

These contexts are adjacent to, but distinct from, the IFPEC application-compilation technique for reconfigurable processor extensions.