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Peter Rugg

Person WIKI v1 · 5/27/2026

Peter Rugg is listed as a co-author of the 2023 IEEE Design & Test paper "Randomized Testing of RISC-V CPUs using Direct Instruction Injection," which presents TestRIG, a randomized testing framework for RISC-V implementations.

Overview

Peter Rugg is identified in the available evidence as a co-author of the paper "Randomized Testing of RISC-V CPUs using Direct Instruction Injection". The paper appears in IEEE Design & Test in 2023 and lists Peter Rugg among its authors alongside Alexandre Joannou, Jonathan Woodruff, Franz A. Fuchs, Marno van der Maas, Matthew Naylor, Michael Roe, Robert N. M. Watson, Peter G. Neumann, and Simon W. Moore. [C1]

Associated work

Randomized Testing of RISC-V CPUs using Direct Instruction Injection

The paper describes TestRIG, short for Testing with Random Instruction Generation, as a testing framework for RISC-V implementations. According to the paper, TestRIG checks equivalence between a formal model and an implementation by generating random instruction sequences, executing those sequences on both the model and the implementation under test, and comparing execution traces in a tandem-execution workflow. [C2]

The paper also introduces Direct Instruction Injection (DII) as the technique used for test injection. In ordinary execution, a processor fetches the next instruction from program memory at the address determined by the program counter; with DII, the test harness supplies the next instruction to execute regardless of the CPU's program counter. [C3]

The authors report using TestRIG to test many standard RISC-V extensions and the experimental CHERI security extension. They also report that TestRIG was easier to use than unit tests, provided more thorough coverage through random generation, and was effective at finding issues not only in instruction semantics but also in the pipeline and data caches. [C4]

Evidence-limited profile

No additional biographical, institutional, or career information about Peter Rugg is present in the supplied evidence. The supported profile is therefore limited to his authorship association with the TestRIG paper and the technical content of that paper. [C1]

LINKED ENTITIES

1 links
Randomized Testing of RISC-V CPUs using Direct Instruction Injection AUTHORED_BY

CITATIONS

4 sources
4 citations
[1] Peter Rugg is listed as a co-author of the paper "Randomized Testing of RISC-V CPUs using Direct Instruction Injection" in IEEE Design & Test, 2023. Randomized Testing of RISC-V CPUs using Direct
[2] The paper describes TestRIG as a testing framework for RISC-V implementations that uses random instruction sequences and tandem execution to compare a formal model with an implementation under test. Randomized Testing of RISC-V CPUs using Direct
[3] The paper describes Direct Instruction Injection as providing the next instruction from the test harness regardless of the CPU program counter. Randomized Testing of RISC-V CPUs using Direct
[4] The paper reports that TestRIG was used to test many standard RISC-V extensions and the experimental CHERI security extension, and that it improved coverage and detected issues in instruction semantics, the pipeline, and data caches. Randomized Testing of RISC-V CPUs using Direct