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Michael Roe

Person WIKI v1 · 5/27/2026

Michael Roe is identified in the available evidence as a co-author of the IEEE Design & Test 2023 paper "Randomized Testing of RISC-V CPUs using Direct Instruction Injection," which describes TestRIG, a randomized testing framework for RISC-V implementations.

Overview

Michael Roe is listed as one of the authors of the paper "Randomized Testing of RISC-V CPUs using Direct Instruction Injection", published in IEEE Design & Test in 2023. The author list includes Alexandre Joannou, Peter Rugg, Jonathan Woodruff, Franz A. Fuchs, Marno van der Maas, Matthew Naylor, Michael Roe, Robert N. M. Watson, Peter G. Neumann, and Simon W. Moore. [C1]

Associated work

The associated paper presents TestRIG—short for Testing with Random Instruction Generation—as a testing framework for RISC-V implementations. The paper explains that TestRIG compares executable formal models, software ISA simulators, and simulated hardware designs by generating random instruction sequences, executing them on both a model and an implementation under test, and comparing execution traces. [C2]

The work also describes Direct Instruction Injection (DII), a technique in which the next instruction executed by the CPU is supplied by the test harness rather than fetched normally according to the program counter. [C3]

Technical context

The paper situates TestRIG in the context of RISC-V model-based verification. It notes that RISC-V has a formal architecture model in the Sail language, which provides a human-readable specification usable for simulation and verification. The paper frames TestRIG as a pragmatic approach for checking equivalence between a model and an implementation when full processor-level formal proof is not yet routinely automated. [C4]

Evidence scope

The available evidence supports Michael Roe's authorship connection to the TestRIG paper and supports technical descriptions of that paper's subject matter. It does not provide additional biographical, institutional, or career details about Michael Roe.

LINKED ENTITIES

1 links
Randomized Testing of RISC-V CPUs using Direct Instruction Injection AUTHORED_BY

CITATIONS

4 sources
4 citations
[1] C1: Michael Roe is listed as a co-author of "Randomized Testing of RISC-V CPUs using Direct Instruction Injection" in IEEE Design & Test, 2023. Randomized Testing of RISC-V CPUs using Direct
[2] C2: The paper presents TestRIG as a randomized testing framework for RISC-V implementations that compares execution traces between models and implementations under test. Randomized Testing of RISC-V CPUs using Direct
[3] C3: The paper describes Direct Instruction Injection as supplying the next instruction from the test harness regardless of the CPU program counter. Randomized Testing of RISC-V CPUs using Direct
[4] C4: The paper states that RISC-V has a Sail formal model and presents TestRIG as a pragmatic equivalence-checking approach because whole-processor formal proof is not yet routinely automated. Randomized Testing of RISC-V CPUs using Direct