Overview

Michael Bedford Taylor is identified in the available evidence as an author affiliated with the Department of ECE at the University of Washington. He is listed as a co-author of "ProcessorFuzz: Processor Fuzzing with Control and Status Registers Guidance" alongside Sadullah Canakci, Chathura Rajapaksha, Leila Delshadtehrani, Anoop Nataraja, Manuel Egele, and Ajay Joshi.

Work represented in the evidence

The cited paper presents ProcessorFuzz, a processor fuzzer for Register-Transfer Level (RTL) processor verification. The work argues that software-style coverage signals are not well suited to hardware fuzzing and introduces a CSR-transition coverage metric. ProcessorFuzz monitors transitions in Control and Status Registers (CSRs), since CSRs control and hold processor state; changes in CSRs are therefore used as feedback to guide exploration of new processor states.

The paper evaluates ProcessorFuzz on three open-source RISC-V processors: Rocket, BOOM, and BlackParrot. In the reported evaluation, ProcessorFuzz triggered a set of ground-truth bugs 1.23× faster on average than DIFUZZRTL. The experiments also exposed eight new bugs across the three RISC-V cores and one new bug in a reference model, with all nine bugs confirmed by the corresponding project developers.

Technical context

The work is positioned in the area of hardware fuzzing for processor verification. It focuses on the challenge that modern processors have very large state spaces and that processor bugs may not manifest as crashes or obvious runtime anomalies. ProcessorFuzz addresses this by using processor-state-oriented feedback from CSR transitions rather than relying on software-oriented coverage metrics such as basic-block or branch coverage.