Marno van der Maas Wiki

Marno van der Maas

Person WIKI v1 · 5/27/2026

Marno van der Maas is listed as a co-author of the IEEE Design & Test 2023 paper "Randomized Testing of RISC-V CPUs using Direct Instruction Injection," which describes TestRIG, a randomized testing framework for RISC-V implementations using Direct Instruction Injection.

Overview

Marno van der Maas is a co-author of the paper "Randomized Testing of RISC-V CPUs using Direct Instruction Injection", published in IEEE Design & Test in 2023. The author list includes Alexandre Joannou, Peter Rugg, Jonathan Woodruff, Franz A. Fuchs, Marno van der Maas, Matthew Naylor, Michael Roe, Robert N. M. Watson, Peter G. Neumann, and Simon W. Moore. [C1]

Associated technical work

The paper presents TestRIG — short for Testing with Random Instruction Generation — as a testing framework for RISC-V implementations. It compares an implementation under test with a formal or executable model by generating random instruction sequences, executing those sequences on both sides, and comparing execution traces in a tandem-execution style. [C2]

A key technique described in the work is Direct Instruction Injection (DII). Instead of fetching the next instruction from program memory using the CPU program counter, DII supplies the next instruction directly from the test harness, regardless of the CPU's program counter. [C3]

The paper reports that TestRIG was used to test many standard RISC-V extensions as well as the experimental CHERI security extension. It also states that TestRIG provided more thorough coverage than unit tests and had replaced the authors' instruction-set-level unit testing for development. [C4]

LINKED ENTITIES

1 links

Randomized Testing of RISC-V CPUs using Direct Instruction Injection AUTHORED_BY

CITATIONS

4 sources

4 citations

[1] Marno van der Maas is a co-author of the paper "Randomized Testing of RISC-V CPUs using Direct Instruction Injection," published in IEEE Design & Test in 2023. Randomized Testing of RISC-V CPUs using Direct Instruction Injection

[2] The paper describes TestRIG as a testing framework for RISC-V implementations that generates random instruction sequences, executes them on a model and implementation under test, and compares execution traces. Randomized Testing of RISC-V CPUs using Direct Instruction Injection

[3] Direct Instruction Injection provides the next instruction from the test harness rather than fetching it from program memory at an address determined by the CPU program counter. Randomized Testing of RISC-V CPUs using Direct Instruction Injection

[4] The paper states that TestRIG was used to test standard RISC-V extensions and the experimental CHERI security extension, and that it replaced the authors' instruction-set-level unit testing for development. Randomized Testing of RISC-V CPUs using Direct Instruction Injection