John L. Hennessy

Person

John L. Hennessy is cited in the provided evidence as co-author, with David A. Patterson, of the 2006 fourth edition of Computer Architecture: A Quantitative Approach. That work is referenced as the source for the DLX instruction set implemented by the VAMP processor in a microprocessor test-program-generation case study.

First seen 5/26/2026

Last seen 5/26/2026

Evidence 2 chunks

Wiki v1

WIKI

Technical profile

John L. Hennessy appears in the evidence as a computer-architecture author cited together with David A. Patterson. The cited bibliographic entry lists John L. Hennessy and David A. Patterson as authors of Computer Architecture, Fourth Edition: A Quantitative Approach, published by Morgan Kaufmann Publishers Inc. in San Francisco, CA, USA, in 2006, with ISBN 0123704901.[C1]

Connection to DLX and VAMP

READ FULL ARTICLE →

NEIGHBORHOOD

No graph connections found for this entity yet. It may appear in future ingestion runs.

explore full graph →

RELATIONSHIPS

1 connections

DLX ISA mentions → 90% 2e

Hennessy and Patterson define the DLX instruction set.

LINKED ENTITIES

1 links

David A. Patterson coauthor The reference list cites John L. Hennessy and David A. Patterson as co-authors of Computer Architecture, Fourth Edition: A Quantitative Approach.

CITATIONS

4 sources

4 citations — click to collapse

[1] John L. Hennessy and David A. Patterson authored Computer Architecture, Fourth Edition: A Quantitative Approach, published by Morgan Kaufmann in 2006 with ISBN 0123704901. Test Program Generation for a Microprocessor: A Case Study

[2] The VAMP processor implements the full DLX instruction set from Hennessy and Patterson. Test Program Generation for a Microprocessor: A Case Study

[3] The DLX instruction set described in the case study includes load and store operations for double words, words, half words, and bytes, as well as shift operations, jump-and-link operations, and arithmetic and logical operations. Test Program Generation for a Microprocessor: A Case Study

[4] The VAMP Isabelle/HOL ISA configuration is described as consisting of a program counter, delayed program counter, general-purpose registers, special-purpose registers, and a memory model. Test Program Generation for a Microprocessor: A Case Study