Georgios Dimitrakopoulos

Person WIKI v1 · 5/28/2026

Georgios Dimitrakopoulos is identified in a 2019 Democritus University of Thrace MSc thesis as an Assistant Professor and the supervisor of work on UVM-based verification of RISC-V superscalar processors.

Georgios Dimitrakopoulos

Georgios Dimitrakopoulos is an academic listed as Assistant Professor and supervisor of Zacharias Takakis's MSc thesis, UVM-based verification of RISC-V superscalar processors: A reinforcement learning approach, dated May 22, 2019.[1]

Academic context

The thesis record is associated with Democritus University of Thrace, the Department of Electrical and Computer Engineering, and the Lab of Integrated Circuits.[2] Within this record, Dimitrakopoulos appears in the supervisory role for the thesis.[1]

Supervised thesis topic

The supervised thesis addressed front-end verification and functional coverage for hardware designs. Its abstract describes two automation techniques for the verification flow: a multi-armed bandit approach for selecting constrained-random or directed test sequences, and a feedback-based mechanism for dynamically adjusting test-application time. The reported experimental target was a non-trivial 2-way superscalar out-of-order RISC-V processor.[3]

Related organization

Democritus University of Thrace

LINKED ENTITIES

1 links

Democritus University of Thrace PART_OF

CITATIONS

3 sources

3 citations

[1] Georgios Dimitrakopoulos was listed as Assistant Professor and supervisor of Zacharias Takakis's MSc thesis titled 'UVM-based verification of RISC-V superscalar processors: A reinforcement learning approach,' dated May 22, 2019. [PDF] UVM-based verification of RISC-V superscalar processors

[2] The thesis record is associated with Democritus University of Thrace, the Department of Electrical and Computer Engineering, and the Lab of Integrated Circuits. [PDF] UVM-based verification of RISC-V superscalar processors

[3] The thesis proposed multi-armed bandit and feedback-based mechanisms to automate test application in verification, with experiments on a 2-way superscalar out-of-order RISC-V processor. [PDF] UVM-based verification of RISC-V superscalar processors