Franco Zappa

Person WIKI v1 · 5/28/2026

Franco Zappa is identified in the available evidence as the professor and advisor for Renato Occhineri's 2023–24 Laurea Magistrale thesis, “UVM based design verification of a RISC-V CPU core.”

Franco Zappa

Franco Zappa is identified in the available evidence as Prof. Franco Zappa, the advisor for Renato Occhineri's Tesi di Laurea Magistrale in Electronics Engineering - Ingegneria Elettronica, titled “UVM based design verification of a RISC-V CPU core.” The thesis title page lists Renato Occhineri as author, Franco Zappa as advisor, and the academic year as 2023–24.

Associated thesis

The thesis advised by Zappa presents a UVM-based verification infrastructure for a RISC-V CPU core. According to its abstract, the work uses UVM and SystemVerilog, integrates open-source tools from the RISC-V toolchain and RISC-V compliance test suite, and includes a random instruction generator, direct tests, benchmarks, and the Spike RISC-V instruction-set simulator to validate instruction execution.

LINKED ENTITIES

1 links

UVM Based Design Verification of a RISC-V CPU Core AUTHORED_BY

CITATIONS

3 sources

3 citations

[1] Franco Zappa is listed as Prof. Franco Zappa and as advisor for Renato Occhineri's Laurea Magistrale thesis. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi

[2] The thesis is titled “UVM based design verification of a RISC-V CPU core,” is in Electronics Engineering - Ingegneria Elettronica, lists Renato Occhineri as author, and is for academic year 2023–24. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi

[3] The thesis abstract describes a UVM-based verification infrastructure for a RISC-V core using UVM, SystemVerilog, open-source RISC-V tools, compliance tests, a random instruction generator, direct tests, benchmarks, and Spike. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi