Flavien Solt
Based on the available evidence, Flavien Solt is documented as an author of the 2024 paper Cascade: CPU Fuzzing via Intricate Program Generation.
Documented publication
- Cascade: CPU Fuzzing via Intricate Program Generation
- Authors: Flavien Solt, Katharina Ceesay-Seitz, and Kaveh Razavi
- Venue: 33rd USENIX Security Symposium (USENIX Security 24)
- Date: August 2024
- Pages: 5341-5358
Affiliation in the cited source
The paper PDF lists Flavien Solt's affiliation as ETH Zurich.
Technical context of the documented work
The cited paper presents Cascade as a CPU fuzzer for RISC-V that generates valid programs of arbitrary length with highly randomized and interdependent control and data flows. The paper states that Cascade uses asymmetric ISA pre-simulation to entangle control flows with data flows, and that this design enables bug detection through program non-termination without runtime overhead. In the reported evaluation, the paper claims 28.2x to 97x more coverage than prior state-of-the-art CPU fuzzers and reports 37 new bugs, including 28 new CVEs, across five RISC-V CPUs. The paper also describes an automated pruning method for reducing bug-triggering programs to a minimal number of instructions.
Scope note
This article is limited to facts explicitly supported by the provided evidence.