David O'Hallaron

Person

David O'Hallaron is referenced in the provided evidence through the Bryant-O’Hallaron computer systems textbook, whose third edition presents Y86-64 pipelined microprocessor designs used in a UCLID5 formal-verification case study.

First seen 5/26/2026

Last seen 5/26/2026

Evidence 2 chunks

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WIKI

David O'Hallaron

David O'Hallaron is associated in the provided evidence with the Bryant-O’Hallaron computer systems textbook. A Carnegie Mellon University technical report on formal verification states that several variants of the Y86-64 pipelined microprocessor presented in the third edition of Bryant and O’Hallaron’s computer systems textbook were formally verified using UCLID5.^[1]

Technical context

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LINKED ENTITIES

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Randal E. Bryant textbook_name_association The report names Randal E. Bryant as author and refers to the Bryant-O’Hallaron computer systems textbook, supporting an association between Bryant and O’Hallaron in that textbook context.

CITATIONS

6 sources

6 citations — click to expand

[1] David O'Hallaron is associated in the provided evidence with the Bryant-O’Hallaron computer systems textbook. Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5

[2] Several variants of the Y86-64 pipelined microprocessor presented in the third edition of Bryant and O’Hallaron’s computer systems textbook were formally verified using UCLID5. Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5

[3] The UCLID5 verification work aimed to provide confidence in the processor designs presented in the Bryant-O’Hallaron textbook and to evaluate UCLID5 as a case study. Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5

[4] The report says the verification succeeded, showing that different pipeline processors generate the same results as the sequential reference model for all possible programs. Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5

[5] Y86-64 adapts features of Intel64/x86-64 while being simpler and intended as a working model for microprocessor design and implementation. Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5

[6] Y86-64 architectural state includes fifteen program registers, condition codes, a program counter, data memory, and a status register; its ISA includes data movement, arithmetic/logical, branch, conditional move, stack, call, and return instructions. Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5