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Claire Wolf

Person WIKI v1 · 5/27/2026

Claire Wolf is cited in technical literature as the specifier of the RISC-V Formal Interface (RVFI), a trace format used for formal verification of RISC-V cores with symbolic instructions.

Overview

Claire Wolf is identified in the available evidence as the person who specified the RISC-V Formal Interface (RVFI). RVFI is described as an existing trace format for formal verification using symbolic instructions.

Technical contribution: RISC-V Formal Interface

The RISC-V Formal Interface exposes selected architecturally significant signals from an implementation. The cited TestRIG paper lists examples including instruction encodings, memory addresses and values, and operand and writeback register indices and values.

RVFI is used as a trace-output interface in verification workflows. In the TestRIG architecture described by the source, RVFI is extended with Direct Instruction Injection (DII): DII provides instruction input, while RVFI provides trace output. Together, RVFI-DII supports interactive verification.

Implementation role in verification systems

The cited source explains that an RVFI interface may export internal signals from an RTL design, or internal variables from a simulator or emulator. For more complex designs such as pipelined or superscalar microarchitectures, implementing RVFI may require preserving state until a commit or write-back stage so that the correct values can be reported.

Significance

Within the evidence provided, Claire Wolf's named contribution is the specification of RVFI, which serves as a formal-verification trace format and a basis for later RVFI-DII verification infrastructure.

CITATIONS

5 sources
5 citations
[1] Claire Wolf specified the RISC-V Formal Interface (RVFI). Randomized Testing of RISC-V CPUs using Direct
[2] RVFI is an existing trace format for formal verification using symbolic instructions. Randomized Testing of RISC-V CPUs using Direct
[3] RVFI exposes architecturally significant signals including instruction encodings, memory addresses or values, and operand and writeback register indices and values. Randomized Testing of RISC-V CPUs using Direct
[4] TestRIG extends RVFI with Direct Instruction Injection, where DII is used for instruction input and RVFI for trace output, supporting interactive verification. Randomized Testing of RISC-V CPUs using Direct
[5] An RVFI interface can export internal signals of an RTL design or internal variables of a simulator or emulator. Randomized Testing of RISC-V CPUs using Direct