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Chathura Rajapaksha

Person WIKI v1 · 5/28/2026

Chathura Rajapaksha is listed as a Boston University ECE co-author of the paper “ProcessorFuzz: Processor Fuzzing with Control and Status Registers Guidance,” which presents a CSR-transition-coverage-guided fuzzer for RTL processor verification.

Overview

Chathura Rajapaksha is listed as a co-author of “ProcessorFuzz: Processor Fuzzing with Control and Status Registers Guidance.” In the author block of that paper, Rajapaksha is associated with the Department of ECE, Boston University and the email address chath@bu.edu.[C1]

Documented publication

ProcessorFuzz

Rajapaksha is one of the authors of ProcessorFuzz, a paper on processor fuzzing for Register-Transfer Level (RTL) verification.[C1] The paper introduces ProcessorFuzz, a processor fuzzer guided by a CSR-transition coverage metric. The paper explains that ProcessorFuzz monitors transitions in Control and Status Registers (CSRs) because CSRs control and hold processor state; CSR transitions therefore indicate new processor states and can guide fuzzing toward unexplored states.[C2]

The work evaluates ProcessorFuzz on three real-world open-source RISC-V processors: Rocket, BOOM, and BlackParrot. According to the paper abstract, ProcessorFuzz triggered ground-truth bugs 1.23× faster on average than DIFUZZRTL, exposed eight new bugs across the three RISC-V cores, and found one new bug in a reference model; the nine bugs were confirmed by the developers of the corresponding projects.[C3]

Technical areas evidenced by the publication

Based on the documented paper, Rajapaksha’s evidenced technical work includes hardware fuzzing, RTL processor verification, CSR-guided coverage metrics, and RISC-V processor testing.[C2]

LINKED ENTITIES

1 links
ProcessorFuzz: Processor Fuzzing with Control and Status Registers Guidance AUTHORED_BY

CITATIONS

3 sources
3 citations
[1] Chathura Rajapaksha is listed as a co-author of “ProcessorFuzz: Processor Fuzzing with Control and Status Registers Guidance” and is associated in the paper author block with the Department of ECE, Boston University and the email address chath@bu.edu. ProcessorFuzz: Processor Fuzzing with Control and Status Registers Guidance
[2] ProcessorFuzz is presented as a processor fuzzer for RTL verification that uses a CSR-transition coverage metric; the paper states that CSRs control and hold processor state and that CSR transitions indicate new processor states. ProcessorFuzz: Processor Fuzzing with Control and Status Registers Guidance
[3] The ProcessorFuzz paper reports evaluation on Rocket, BOOM, and BlackParrot; it states that ProcessorFuzz triggered ground-truth bugs 1.23× faster on average than DIFUZZRTL, exposed eight new bugs across the three RISC-V cores, and found one new bug in a reference model, with all nine confirmed by project developers. ProcessorFuzz: Processor Fuzzing with Control and Status Registers Guidance