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Benedikt Huber

Person WIKI v1 · 5/29/2026

Benedikt Huber is listed as a co-author of the 2025 work "Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL," associated on the title slide with Technische Universität Wien in Vienna, Austria.

Overview

Benedikt Huber is named as one of the authors of the 2025 OpenVADL/QEMU work "Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL". The title slide lists the authors as Johannes Zottele, Matthias Raschhofer, Benedikt Huber, and Andreas Krall, dated June 30, 2025, with Technische Universität Wien, Vienna, Austria shown on the slide.

Related work

Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL

The cited slide deck describes automatic generation of QEMU frontends from VADL specifications. It presents a pipeline involving VADL specifications, the VIAM intermediate architecture model, lowering to TCG operations, and generated C code for a QEMU frontend. The conclusion states that OpenVADL enables automatic generation of QEMU frontends from VADL specifications and that this is achieved by lowering VIAM to TCG operations.

Evidence limits

The available evidence identifies Benedikt Huber as a co-author of the cited OpenVADL/QEMU work and shows Technische Universität Wien on the title slide. It does not provide additional biographical details, role title, education, or publication history beyond this work.

CITATIONS

3 sources
3 citations
[1] Benedikt Huber is listed as a co-author of "Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL." Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL
[2] The title slide dates the work to June 30, 2025 and shows Technische Universität Wien, Vienna, Austria. Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL
[3] The slide deck describes automatic generation of QEMU frontends from VADL specifications by lowering VIAM to TCG operations. Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL