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Ajay Joshi

Person WIKI v1 · 5/28/2026

Ajay Joshi is listed as a Boston University Department of ECE author of the paper “ProcessorFuzz: Processor Fuzzing with Control and Status Registers Guidance,” which presents a CSR-transition-coverage-guided processor fuzzer for RTL verification.

Overview

Ajay Joshi is listed as an author affiliated with the Department of ECE at Boston University on the paper “ProcessorFuzz: Processor Fuzzing with Control and Status Registers Guidance.”

Research represented in the available evidence

The available evidence links Joshi to ProcessorFuzz, a processor fuzzing work for Register-Transfer Level (RTL) verification. The paper presents a processor fuzzer guided by a CSR-transition coverage metric: ProcessorFuzz monitors transitions in Control and Status Registers (CSRs), which the paper describes as controlling and holding processor state, so that CSR transitions can guide exploration of new processor states.

The paper reports evaluation on three open-source RISC-V processors—Rocket, BOOM, and BlackParrot—and states that ProcessorFuzz triggered ground-truth bugs 1.23× faster on average than DIFUZZRTL. It also reports exposing eight new bugs across the three RISC-V cores and one new bug in a reference model, with all nine bugs confirmed by the corresponding project developers.

CITATIONS

3 sources
3 citations
[1] Ajay Joshi is listed as an author of “ProcessorFuzz: Processor Fuzzing with Control and Status Registers Guidance” and is affiliated with the Department of ECE at Boston University in the paper author block. ProcessorFuzz: Processor Fuzzing with Control and Status Registers Guidance
[2] ProcessorFuzz is presented as a processor fuzzer for RTL verification guided by a novel CSR-transition coverage metric that monitors Control and Status Register transitions to explore processor states. ProcessorFuzz: Processor Fuzzing with Control and Status Registers Guidance
[3] The paper reports evaluation on Rocket, BOOM, and BlackParrot; triggering ground-truth bugs 1.23× faster on average than DIFUZZRTL; and exposing eight new RISC-V core bugs plus one reference-model bug, all confirmed by developers. ProcessorFuzz: Processor Fuzzing with Control and Status Registers Guidance