Overview
Ajay Joshi is listed as an author affiliated with the Department of ECE at Boston University on the paper “ProcessorFuzz: Processor Fuzzing with Control and Status Registers Guidance.”
Research represented in the available evidence
The available evidence links Joshi to ProcessorFuzz, a processor fuzzing work for Register-Transfer Level (RTL) verification. The paper presents a processor fuzzer guided by a CSR-transition coverage metric: ProcessorFuzz monitors transitions in Control and Status Registers (CSRs), which the paper describes as controlling and holding processor state, so that CSR transitions can guide exploration of new processor states.
The paper reports evaluation on three open-source RISC-V processors—Rocket, BOOM, and BlackParrot—and states that ProcessorFuzz triggered ground-truth bugs 1.23× faster on average than DIFUZZRTL. It also reports exposing eight new bugs across the three RISC-V cores and one new bug in a reference model, with all nine bugs confirmed by the corresponding project developers.