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Fuzzing Hardware Like Software

Paper WIKI v1 · 5/26/2026

“Fuzzing Hardware Like Software” is a 2021 CoRR paper by Timothy Trippel, Kang G. Shin, Alex Chernyakhovsky, Garret Kelly, Dominic Rizzo, and Matthew Hicks. In the hardware-verification literature, it is identified as a fuzzing-based approach focused on individual hardware IP blocks such as AES or HMAC, using TileLink bus-protocol instructions for its testbench implementation.

Overview

Fuzzing Hardware Like Software is a paper published as a CoRR preprint in 2021 with arXiv identifier 2102.02308. The cited bibliographic entry lists the authors as Timothy Trippel, Kang G. Shin, Alex Chernyakhovsky, Garret Kelly, Dominic Rizzo, and Matthew Hicks. [C1]

Position in hardware-fuzzing research

A later paper, Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing, places Fuzzing Hardware Like Software among the small number of approaches that apply fuzzing to hardware verification. [C2]

In that comparison, Fuzzing Hardware Like Software is characterized as targeting individual IP blocks—examples given are AES and HMAC hardware peripherals—rather than verifying an entire processor core. [C3]

Testbench input model

The same comparison states that the approach generates TileLink bus protocol instructions for its testbench implementation. It contrasts this with approaches that generate processor-core instructions directly, noting that bus-protocol generation implies a bus-centric input model rather than direct mutation of binary processor instructions. [C4]

Bibliographic details

  • Title: Fuzzing Hardware Like Software [C1]
  • Authors: Timothy Trippel, Kang G. Shin, Alex Chernyakhovsky, Garret Kelly, Dominic Rizzo, and Matthew Hicks [C1]
  • Venue/type: CoRR preprint [C1]
  • Year: 2021 [C1]
  • Identifier: arXiv:2102.02308 [C1]
  • URL: https://arxiv.org/abs/2102.02308 [C1]

CITATIONS

4 sources
4 citations
[1] C1: Bibliographic metadata for “Fuzzing Hardware Like Software”: authors, year, CoRR venue, arXiv identifier, and arXiv URL. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing
[2] C2: “Fuzzing Hardware Like Software” is identified in later work as one of the few fuzzing approaches for hardware verification. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing
[3] C3: The approach is described as verifying individual IP blocks such as AES or HMAC hardware peripherals rather than an entire processor core. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing
[4] C4: The approach is described as generating TileLink bus protocol instructions for its testbench implementation, in contrast to approaches that generate processor-core instructions directly. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing