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Siemens EDA

Organization WIKI v1 · 9/9/2026

Siemens EDA is the electronic design automation division referenced in industry contexts as a provider of verification technologies for RISC-V processor design, including hardware-assisted verification (virtual prototypes, emulation, and hardware prototyping) and SystemVerilog simulation environments used in standards-based RISC-V verification flows such as RVVI and ImperasDV integration.

Siemens EDA

Overview

Siemens EDA is identified in industry sources as an electronic design automation organization that supplies verification technologies used in advanced processor and SoC design flows, including flows targeting the RISC-V instruction set architecture.

Role in RISC-V Verification

Siemens EDA is referenced as one of the leading EDA vendors whose SystemVerilog simulation environments are integrated with standards-based RISC-V verification IP and methodologies.

  • Coverage-driven verification and lock-step-compare approaches for RISC-V processors rely on SystemVerilog test bench environments provided by major EDA vendors, including Siemens EDA, alongside Cadence and Synopsys.
  • ImperasDV verification IP provides design flow integration for the leading EDA SystemVerilog environments, explicitly naming "Cadence, Siemens EDA, and Synopsys" as the supported vendors.
  • RVVI (RISC-V Verification Interface) usage examples describe SystemVerilog simulation environments from "Cadence, Synopsys, Siemens EDA respectively" as target platforms for RVVI-based test benches.

Hardware-Assisted Verification Perspective

Siemens EDA has publicly commented on RISC-V micro-architectural verification, emphasizing the role of hardware-assisted verification technologies:

  • Andy Meier, principal product marketing manager for Siemens EDA, described hardware-assisted verification — including virtual prototype capabilities, emulation, and hardware prototyping — as critical components in the overall verification flow for RISC-V, helping ensure that micro-architectural decisions do not have negative impacts on power and performance tradeoffs.

Industry Events

  • Siemens EDA is listed as a participant/exhibitor at DVCon Japan 2026, scheduled for Thursday, September 10, 2026 in Yokohama, Kanagawa.

Related Standards and Ecosystems

Siemens EDA environments appear in the context of the following RISC-V verification standards and projects:

  • RVVI (RISC-V Verification Interface) — a draft open standard for RISC-V test bench reuse, with Siemens EDA simulators among the supported SystemVerilog environments.
  • ImperasDV — verification IP with design flow integration targeting Siemens EDA SystemVerilog environments.
  • OpenHW Group CORE-V verification — open-source RISC-V verification projects that integrate with commercial EDA simulation flows.

LINKED ENTITIES

1 links
DVCon Japan 2026 MENTIONS

CITATIONS

4 sources
4 citations
[1] Siemens EDA is listed as a participant at DVCon Japan 2026 on September 10, 2026 in Yokohama, Kanagawa. DVCon Japan 2026 listing
[2] Imperas provides examples of use of RVVI with its ImperasDV product with SystemVerilog for use with environments from Cadence, Synopsys, and Siemens EDA. riscv-verification/RVVI
[3] ImperasDV provides integrated solutions for RISC-V processor verification combined with design flow integration for the leading EDA SystemVerilog environments with Cadence, Siemens EDA, and Synopsys. Survey of Verification of RISC-V Processors
[4] Andy Meier, principal product marketing manager for Siemens EDA, stated that hardware-assisted verification such as virtual prototype capabilities, emulation, and hardware prototyping are critical components in the overall RISC-V verification flow. RISC-V Micro-Architectural Verification