Overview
UC Santa Cruz appears in the available technical evidence as an academic affiliation for authors contributing to processor-verification research. In the 2021 MICRO-54 paper Effective Processor Verification with Logic Fuzzer Enhanced Co-simulation, Nursultan Kabylkas and Jose Renau are listed with UC Santa Cruz affiliations in Santa Cruz, California, USA.
Research context in the evidence
The cited paper addresses RISC-V processor verification and presents tools intended to improve verification productivity and expose more processor bugs before production. The paper describes Logic Fuzzer (LF) as a tool that randomizes selected design-under-test states or control signals where functionality is not affected, thereby exercising more microarchitectural states without requiring additional verification tests. It also presents Dromajo as an RV64GC emulator designed for RISC-V co-simulation purposes.
Associated people
- Nursultan Kabylkas — listed as affiliated with UC Santa Cruz and using a
ucsc.eduemail address in the paper. - Jose Renau — listed as affiliated with UC Santa Cruz and using a
ucsc.eduemail address in the paper.