Imperas

Imperas is an organization whose primary focus in the RISC-V ecosystem is on simulation-based processor verification. It produces both free reference simulation models and commercial verification IP and methodologies used by RISC-V core developers.

Free Reference Simulation Models

Imperas maintains a free RISC-V reference simulator that is widely used as a compliance and trace-comparison baseline:

• riscvOVPsim – a free Imperas RISC-V reference model distributed from GitHub. It is used in a simple log/signature-file comparison flow, where the same cross-compiled application ELF is run against an RISC-V.org signature file on the reference model.
• riscvOVPsimPlus – an extended free reference model that builds on riscvOVPsim with fully configurable instruction trace, GDB/Eclipse debug support, memory configuration options, and additional architectural features including CLIC, Debug Module/Mode, multi-hart, H-hypervisor simulation, and the ratified ISA extensions V (vector), B (bitmanip), K (scalar crypto), and Zfinx, plus the near-ratified P-SIMD/DSP and Zmmul extensions.

These models are used in the post-simulation trace-compare method, in which an LLVM-built CPU+Memory RISCV.elf is executed on both the RTL under test and the ISS reference, producing separate Imperas.log files whose program counter (PC), control and status registers (CSRs), general-purpose registers (GPRs), and other internal states are compared instruction by instruction. Immediate comparison enables debug examination directly at failure, though the technique does not work for asynchronous events, control flow, and hardware real-time effects.

Commercial Verification Products: ImperasDV

ImperasDV provides integrated solutions for RISC-V processor verification for both RTL bug detection and analysis. It is designed to be combined with leading EDA SystemVerilog environments from Cadence, Siemens EDA, and Synopsys.

Key ImperasDV Verification IP options include:

• riscvISACOV – a set of SystemVerilog source functional coverage libraries covering all ratified instruction extensions, including interrupts and dynamic effects.
• Privilege-mode libraries intended to be used together with the effects of asynchronous events during verification.
• Architectural validation test suites for the RV32E, RV64E, Zc, and Zmmul specifications.

ImperasDV is used to support the sync-lock-step-compare (step-and-compare) verification approach and the async-lock-step-compare approach, which extends sync-lock-step-compare with asynchronous events. The async flow is considered the gold standard in dynamic (simulation-based) verification and is the best DV environment currently available for RISC-V. Imperas provides examples of RVVI use with ImperasDV in C/C++ for Verilator designs and in SystemVerilog for use with Xcelium, VCS, and Questa from Cadence, Synopsys, and Siemens EDA respectively.

Standards-Based Verification: RVVI

The RISC-V Verification Interface (RVVI) is a draft open standard intended to make testbenches, test generators, functional coverage, and other testing methodologies reusable. Imperas supports RVVI within its ImperasDV product and provides example integrations as described above.

Authored Tools

The Imperas organization authors or maintains the following RISC-V verification tools (see related entities):

• riscv-ovpsim – the Imperas RISC-V OVPsim reference simulator toolchain (related entity, AUTHORED_BY Imperas).
• imperas-riscv-tests – the Imperas RISC-V test suite, mirrored from the upstream GitHub repository riscv-ovpsim/imperas-riscv-tests (related entity, AUTHORED_BY Imperas). A mirror snapshot is tagged v20230724.

Role in the RISC-V Verification Landscape

Imperas's free reference models (riscvOVPsim, riscvOVPsimPlus) are commonly used for compliance signature checking and post-simulation trace comparison, while ImperasDV provides the commercial, standards-aligned (RVVI) verification IP and step-and-compare / async-lock-step-compare flows used in industry RISC-V core verification projects.