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European Processor Initiative

Organization WIKI v1 · 5/27/2026

The European Processor Initiative (EPI) is described in the provided evidence as a project conceived to create the first European processor and accelerators, with an emphasis on independence from non-European computing technologies. Evidence from a paper on functional verification reports an EPI-context RISC-V vector accelerator that was successfully taped out, with Barcelona Supercomputing Center developing the Vector Accelerator and SemiDynamics designing the scalar RISC-V core to which it connected.

Overview

The European Processor Initiative (EPI) is a project conceived to create the first European processor and accelerators. The provided evidence frames EPI as part of a broader effort to provide independence from non-European computing technologies. [Project scope and independence]

Accelerator context

A paper titled "Functional Verification of a RISC-V Vector Accelerator" reports functional verification work for an academic RISC-V-based vector accelerator that was successfully taped out in the context of EPI. The accelerator is described as a novel, decoupled vector accelerator implementing version 0.7.1 of the RISC-V Vector Extension and connected to a scalar processor core through the Open Vector Interface (OVI). [EPI accelerator tape-out and interface]

Partner and component roles

The evidence states that many partners were involved in EPI development. In the cited accelerator work:

  • Barcelona Supercomputing Center (BSC) developed the Vector Accelerator.
  • The Vector Accelerator was directly connected to a scalar RISC-V core designed by SemiDynamics.
  • Top-level integration of the test chip was done by EXTOLL.
  • Tape-out coordination was performed by Fraunhofer. [Partner and component roles]

Vector Processing Unit characteristics

The Vector Processing Unit (VPU) described in the evidence is based on the RISC-V ISA Vector Extension 0.7.1v. It has eight vector lanes and supports vectors up to 256 elements of 64 bits each, for a total maximum vector length of 16 Kb. The VPU includes 32 logical and 40 physical vector registers. Each lane includes one fused multiply-add unit capable of two double-precision operations per cycle, yielding a stated maximum throughput of 16 double-precision floating-point operations per cycle across the eight lanes. [VPU architectural characteristics]

The VPU supports 64-bit and 32-bit floating-point vector operations and 64-bit, 32-bit, 16-bit, and 8-bit integer vector operations. Memory operations are described as having limited out-of-order capability, mostly between arithmetic and memory operations. [VPU operation support]

Verification results reported in the evidence

The cited paper reports an industrial-grade verification approach using a UVM testbench, a reference model, assertions, coverage, constrained-random binaries, C programs, and automated testing/regression infrastructure. The authors report finding 3005 errors and reaching 95.79% functional coverage during the verification process. [Verification infrastructure and results]

LINKED ENTITIES

3 links
Functional Verification of a RISC-V Vector Accelerator MENTIONS
Barcelona Supercomputing Center PART_OF
SemiDynamics PART_OF

CITATIONS

6 sources
6 citations
[1] Project scope and independence Functional Verification of a RISC-V Vector Accelerator
[2] EPI accelerator tape-out and interface Functional Verification of a RISC-V Vector Accelerator
[3] Partner and component roles Functional Verification of a RISC-V Vector Accelerator
[4] VPU architectural characteristics Functional Verification of a RISC-V Vector Accelerator
[5] VPU operation support Functional Verification of a RISC-V Vector Accelerator
[6] Verification infrastructure and results Functional Verification of a RISC-V Vector Accelerator