Overview

Barcelona Supercomputing Center (BSC) appears in the supplied evidence as the institutional affiliation for work on the functional verification of a RISC-V vector accelerator. The paper Functional Verification of a RISC-V Vector Accelerator lists a “Validation Team” in the “Computer Sciences Department” at Barcelona Supercomputing Center, includes multiple author email affiliations at bsc.es, and notes that the work was done while the authors were affiliated with Barcelona Supercomputing Center. [citation: BSC affiliation in verification paper]

Role in the European Processor Initiative

The evidence describes the European Processor Initiative (EPI) as a project intended to create the first European processor and accelerators. Within that project context, BSC is described as having developed the Vector Accelerator, which was to be directly connected to a scalar RISC-V core designed by SemiDynamics. The same passage says that EXTOLL handled top-level test-chip integration and Fraunhofer coordinated tape-out. [citation: BSC role in EPI vector accelerator]

RISC-V vector accelerator verification work

The paper reports functional verification work for an academic RISC-V-based vector accelerator that was successfully taped out in the context of the European Processor Initiative. The verification infrastructure used a UVM environment and step-by-step co-simulation of vector instructions, with the Spike instruction-set simulator used as a reference model. The authors also report automated constrained-random test generation, simulation and error reporting, and CI/CD infrastructure for validating a complex design connected to a scalar core through a custom interface. [citation: Verification infrastructure and EPI tape-out]

The paper states that the verification process found 3005 errors and reached 95.79% functional coverage. It identifies the main contributions as an industrial-grade verification approach, a common UVM testbench for a novel interface and large-scale RTL project, instruction-result comparison against a reference model via co-simulation, and automated testing/regression infrastructure. [citation: Verification results and contributions]

Vector Processing Unit technical characteristics

The Vector Processing Unit (VPU) discussed in the evidence is described as based on RISC-V ISA Vector extension 0.7.1v. It has eight vector lanes and supports vectors up to 256 elements of 64 bits each, for a total maximum vector length of 16 Kb. It has 32 logical and 40 physical vector registers. Each lane includes one fused multiply-add unit capable of two double-precision operations per cycle, giving a stated maximum throughput of 16 double-precision floating-point operations per cycle. [citation: VPU architecture]

The VPU supports 64-bit and 32-bit floating-point vector operations, as well as 64-bit, 32-bit, 16-bit, and 8-bit integer vector operations. The evidence also states that memory operations have limited out-of-order capability, mostly between arithmetic and memory operations. [citation: VPU operation support]

Interfaces and system context

The vector accelerator was connected to a scalar processor core through the Open Vector Interface (OVI). The scalar core executes scalar instructions and sends vector instructions to the VPU, while memory accesses for vector memory operations are performed by the core through OVI. [citation: VPU interface and scalar-core interaction]