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x86-64

ISA WIKI v1 · 5/25/2026

x86-64 is the informal name for the Intel64 instruction set architecture. The provided evidence identifies it as an ISA with 16 program registers and notes several features adapted by the simplified educational Y86-64 ISA.

Overview

x86-64 is identified in the evidence as the informal name for the Intel64 instruction set architecture. The Y86-64 instruction set architecture is described as adapting many features of Intel64, while being much simpler and intended as a working model for understanding microprocessor design and implementation rather than as a full processor implementation.

Architectural characteristics noted in the evidence

The evidence states that the x86-64 ISA has 16 program registers. In comparison, Y86-64 supports 15 registers by omitting %r15, a simplification used to make room in a four-bit register field for a special no-register value.

The evidence also describes x86-64-related instruction behavior by comparison with Y86-64:

  • The x86-64 data movement instruction movq is split in Y86-64 into four cases: register-to-register, immediate-to-register, register-to-memory, and memory-to-register.
  • Stack operations are described as matching x86-64 behavior: pushing first decrements the stack pointer by eight and then writes a word at the stack-pointer address; popping reads the top word and then increments the stack pointer by eight.

Relationship to Y86-64

Y86-64 is a simplified ISA that adapts many features of Intel64, known informally as x86-64. The cited report uses Y86-64 as a model for processor design and verification, not as a complete x86-64 implementation.

LINKED ENTITIES

1 links

CITATIONS

5 sources
5 citations
[2] The x86-64 ISA has 16 program registers. Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5
[3] Y86-64 adapts many features of Intel64/x86-64 but is much simpler and is intended as a working model for microprocessor design and implementation rather than a full processor implementation. Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5
[4] The x86-64 data movement instruction movq is split in Y86-64 into register-register, immediate-register, register-memory, and memory-register forms. Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5
[5] As with x86-64, stack pushing decrements the stack pointer by eight before writing a word, and popping reads the top word before incrementing the stack pointer by eight. Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5