RVA23

Overview

RVA23 is identified in the supplied evidence as one of the newer RISC-V profiles supported by a RISC-V verification flow. The evidence mentions RVA23 together with RVA22 under “future-ready compliance,” indicating that the verification methodology is intended to remain aligned with newer RISC-V profile requirements.^[1]

Verification context

The available evidence discusses RVA23 in the context of RISC-V processor verification. The described methodology combines constrained-random stimulus with directed test suites to improve coverage closure, debug efficiency, reproducibility, and portability across simulation, emulation, FPGA prototyping, and silicon.^[2]

Within that flow, support for new RISC-V profiles such as RVA23 is presented alongside coverage of critical privilege-related specification areas, including MMU, PMP, hypervisor, and vector extensions. The evidence does not define the detailed technical contents of the RVA23 profile itself; it only establishes that the flow supports it as part of future-ready RISC-V compliance work.^[3]

Notes on scope

No additional architectural requirements, mandatory extensions, or conformance rules for RVA23 are specified in the supplied evidence. Claims about the exact contents of RVA23 should therefore be sourced from the official RISC-V profile specification before being added here.

^[1]: Evidence chunk 5a6d1aa2-97b7-4af3-9769-bbfb42afbb37 identifies RVA23 as one of the new RISC-V profiles supported by the flow. ^[2]: Evidence chunk 5a6d1aa2-97b7-4af3-9769-bbfb42afbb37 describes the hybrid RISC-V verification methodology and its benefits. ^[3]: Evidence chunk 5a6d1aa2-97b7-4af3-9769-bbfb42afbb37 states that the flow supports new RISC-V profiles and covers MMU, PMP, hypervisor, and vector extensions.