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FLI.H

ISA WIKI v1 · 9/27/2026

FLI.H is a RISC-V floating-point load-immediate instruction defined as part of the Zfa extension. It loads a predetermined 16-bit half-precision floating-point constant into a floating-point register. The instruction is supported by the sail-riscv formal specification.

FLI.H

Overview

FLI.H (Float Load Immediate, Half-precision) is a RISC-V instruction that writes a predefined half-precision (16-bit, FP16) floating-point constant into a floating-point register rd. It is one of the FLI variants defined by the RISC-V Zfa extension, alongside FLI.S (single-precision) and FLI.D (double-precision).

Classification

  • ISA extension: Zfa
  • Instruction family: FLI (Float Load Immediate)
  • Operand precision: Half-precision floating-point (binary16)

Semantics

FLI.H loads one of a small, architecture-defined set of half-precision floating-point constants (for example, ±1.0, ±0.5, the smallest positive normal, the largest subnormal, ±∞, and signaling/quiet NaNs) into floating-point register rd. The specific constant chosen is encoded in an immediate field of the instruction. The values used by FLI.H mirror those defined for FLI.S and FLI.D, simply represented in FP16 format.

Implementation

The sail-riscv formal specification for RISC-V implements FLI.H as part of its support for the Zfa extension. It was introduced together with the rest of the Zfa instruction set in the sail-riscv commit that added Zfa support (excluding quad-precision).

  • Implementation artifact: sail-riscv
  • Relation: sail-riscv IMPLEMENTS FLI.H (as part of Zfa)
  • Zfa scope in sail-riscv: FLI.[HSD], FMINM/FMAXM.[HSD], FROUND/FROUNDNX.[HSD], FMVH.X.D, FMVP.D.X, FLEQ/FLTQ.[HSD], FCVTMOD.W.D (quad-precision excluded)

Related Instructions (Zfa family)

  • FLI.S — load-immediate, single-precision
  • FLI.D — load-immediate, double-precision
  • FMINM.[HSD], FMAXM.[HSD] — min/max with alternate NaN handling
  • FROUND.[HSD], FROUNDNX.[HSD] — round to integer in FP register (with/without inexact)
  • FMVH.X.D, FMVP.D.X — RV32 double-precision move helpers
  • FLEQ.[HSD], FLTQ.[HSD] — comparisons that do not raise invalid on qNaN
  • FCVTMOD.W.D — convert double to integer with truncated modulus semantics

References

  • sail-riscv commit f2d8e1b9 — "Add Zfa extension support (excl. quad-precision)", introducing FLI.[HSD] and the rest of the Zfa instruction set.

LINKED ENTITIES

2 links
Zfa PART_OF
sail-riscv IMPLEMENTS

CITATIONS

3 sources
3 citations
[1] FLI.H is part of the Zfa RISC-V extension. Add Zfa extension support (excl. quad-precision) — sail-riscv commit f2d8e1b9
[2] sail-riscv implements FLI.H along with FLI.S and FLI.D as part of Zfa support. Add Zfa extension support (excl. quad-precision) — sail-riscv commit f2d8e1b9
[3] The Zfa support added by the referenced commit explicitly excludes quad-precision and covers FLI.[HSD], FMINM/FMAXM.[HSD], FROUND/FROUNDNX.[HSD], FMVH.X.D, FMVP.D.X, FLEQ/FLTQ.[HSD], and FCVTMOD.W.D. Add Zfa extension support (excl. quad-precision) — sail-riscv commit f2d8e1b9