FLI.D
Overview
FLI.D is a floating-point load-immediate instruction introduced as part of the RISC-V Zfa extension. It writes a constant floating-point value to the double-precision (.D) floating-point register rd.
Extension Context
FLI.D is one of the FLI.[HSD] variants added when Zfa extension support (excluding quad-precision) was introduced into the sail-riscv formal model. The broader Zfa support added in that change set includes infrastructure for the Zfa extension (such as an existence macro) as well as implementations of:
FLI.[HSD]— load floating-point immediate (half / single / double precision).FMINM.[HSD]/FMAXM.[HSD]— min/max with adjusted NaN-handling semantics.FROUND.[HSD]/FROUNDNX.[HSD]— round-to-integer instructions, with theNXvariant also signaling inexact.FMVH.X.D/FMVP.D.X— RV32-only moves between pairs of integer registers and a double-precision FP register.FLEQ.[HSD]/FLTQ.[HSD]— quiet comparison instructions that do not signal invalid on quiet NaN inputs.FCVTMOD.W.D— bounded conversion from double to signed word.
Implementation
FLI.D is implemented in the sail-riscv formal specification as part of the Zfa instruction set. The commit that adds Zfa support to sail-riscv enumerates FLI.[HSD] among the instructions introduced, together with the rest of the Zfa instruction set listed above.
Relationships
- Part of: Zfa (RISC-V extension for additional floating-point instructions).
- Implemented in: sail-riscv — the Sail formal specification of RISC-V, which models
FLI.Dalongside the rest of the Zfa extension.
See Also
- Zfa — the parent extension providing the
FLI.[HSD]family. - sail-riscv — the formal-model code artifact in which
FLI.Dis implemented.