Overview

DLX ISA is an instruction set identified in the evidence through the VAMP processor case study. The source states that VAMP "implements the full DLX instruction set from Hennessy and Patterson." [C1]

Instruction coverage noted in the evidence

The cited case study describes the DLX instruction set implemented by VAMP as including:

• load and store operations for double words, words, half words, and bytes; [C2]
• shift operations; [C2]
• jump-and-link operations; [C2]
• arithmetic and logical operations. [C2]

Formal modeling context

The DLX implementation appears in the context of the VAMP processor and the Verisoft project. The case study says that an Isabelle/HOL programmer's-model specification of VAMP was introduced, with the processor defined as a set of transitions over Instruction Set Architecture configurations. [C3]

In that model, an ISA configuration is composed of five elements: a program counter (pcp), a delayed program counter (dcp), general-purpose registers (gprs), special-purpose registers (sprs), and a memory model (mm). [C3]

Register and memory model in the cited VAMP ISA configuration

The cited VAMP ISA configuration is described as follows:

• pcp: a 30-bit program-counter register containing the address of the next instruction to be executed, used to fetch an instruction without altering the current instruction's execution. [C3]
• dcp: a 30-bit delayed-program-counter register associated with the currently executed instruction; the evidence says dcp is kept unchanged until the end of current-instruction execution while the next instruction is fetched through pcp. [C3]
• gprs: 32 general-purpose 32-bit registers, addressed by indices 0 through 31, with the first register always set to 0. [C3]
• sprs: 32 special-purpose 32-bit registers used for particular tasks; the first is described as a status register containing interrupt masks, and some are used as flag or condition registers. [C3]
• mm: a 2^32-byte addressable memory model, with caching and virtual-memory infrastructure implemented in the VAMP system. [C3]

Assembler-level abstraction

The case study also describes an assembly-language model that abstracts the VAMP ISA for test specifications and experiments. This abstraction avoids bit-vector representations by representing addresses as natural numbers and register and memory contents as integers. [C4]

At the assembler-model level, instructions are represented using readable abstract datatypes, address translation is hidden, computation occurs in a linear virtual-memory space, and interrupts are not visible. The assembler configuration abstracts the ISA configuration with fields for pcp, dcp, gprs, sprs, and mm, where the register files are lists of integers and memory is modeled as a mapping from natural numbers to integers. [C4]

Source association

The cited paper associates the DLX instruction set with John L. Hennessy and David A. Patterson and lists Computer Architecture, Fourth Edition: A Quantitative Approach as reference [15]. [C5]