VAMP assembler model (Isabelle/HOL)

CodeArtifact

The VAMP assembler model is an Isabelle/HOL formalization of the assembly-level instruction-set behavior of the Verified Architecture Microprocessor. It represents processor configurations with program counters, register files, and memory; defines the instruction set as an Isabelle datatype; and gives operational semantics through exec_instr and Step functions. In the cited case study, the model is reused with HOL-TestGen to generate unit and sequence tests for processor conformance.

First seen 5/26/2026

Last seen 5/26/2026

Evidence 5 chunks

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Overview

The VAMP assembler model is the assembly-level model of the Verified Architecture Microprocessor (VAMP), a realistic RISC processor inspired by IBM's G5 architecture. In the Verisoft project, formal models for the processor and a small operating system were developed in Isabelle/HOL, and the processor model was reused for model-based generation of test programs that check whether hardware conforms to the VAMP model.^[1]

Within the Verisoft system architecture, the relevant layer is the hardware layer at the assembly level, called VAMPasm, described as the instruction set of VAMP.^[2]

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RELATIONSHIPS

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Test Program Generation for a Microprocessor: A Case-Study ← uses 100% 2e

The paper uses the VAMP assembler model as the basis for test generation.

exec_instr function ← part of 100% 1e

The exec_instr function is part of the VAMP assembler model.

ASMcoret record ← part of 100% 1e

The ASMcoret record is part of the VAMP assembler model.

instr datatype ← part of 100% 1e

The instr datatype is part of the VAMP assembler model.

is_ASMcore predicate ← part of 100% 1e

The is_ASMcore predicate is part of the VAMP assembler model.

VAMP SML executable model ← derived from 100% 1e

The SML executable model is generated from the Isabelle/HOL model.

LINKED ENTITIES

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HOL-TestGen used_with The evidence states that HOL-TestGen is used to generate test sequences from the VAMP model and later reports generated test scripts and executable testers.

CITATIONS

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9 citations — click to expand

[1] VAMP is a realistic RISC processor inspired by IBM's G5 architecture; in Verisoft, formal models for the processor and a small operating system were developed in Isabelle/HOL and the processor model was reused for model-based test generation. Test Program Generation for a Microprocessor: A Case Study

[2] The relevant Verisoft hardware-layer model is the assembly-level VAMPasm instruction set of VAMP. Test Program Generation for a Microprocessor: A Case Study

[3] The assembler model represents register files as integer lists, defines an ASMcoret record with dpc, pcp, gprs, sprs, and mm fields, and uses is_ASMcore to require 32 general-purpose and 32 special-purpose registers plus valid register and memory contents. Test Program Generation for a Microprocessor: A Case Study

[4] The instruction set is an Isabelle datatype instr; exec_instr defines instruction semantics; and Step executes the current instruction selected from the delayed program counter. Test Program Generation for a Microprocessor: A Case Study

[5] The assembler model is more abstract than the processor model and hides details such as interrupt handling, virtual memory and caching, pipelining, and instruction reordering; it is used in black-box testing to check processor behavior against the assembler model. Test Program Generation for a Microprocessor: A Case Study

[6] The case study applies model-based unit testing and sequence testing, using unit tests for individual instructions and sequence tests for instruction sequences, and studies load/store, arithmetic, logic, and control-flow instruction groups. Test Program Generation for a Microprocessor: A Case Study

[7] The unit-test conformance specification compares the system under test with exec_instr using a relation that compares registers and the top k memory cells, with SUT replaced during execution by the actual system under test. Test Program Generation for a Microprocessor: A Case Study

[8] Generated SML code for VAMP includes a generated instr datatype and functions such as int_add, int_sub, cell2data, exec_instr, sigma_0, and execInstrs; HOL-TestGen generated 585 test cases for each of load/store and arithmetic sequences, and mutations in int_add, int_sub, and cell2data led to 282 arithmetic failures and 531 load/store failures. Test Program Generation for a Microprocessor: A Case Study

[9] The approach is presented as integrating test-program generation into an existing verification tool chain while reusing existing verification models, unlike approaches based on independently developed dedicated test models. Test Program Generation for a Microprocessor: A Case Study