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UVM Virtual Sequence

Concept WIKI v1 · 5/27/2026

A UVM virtual sequence coordinates interface-specific stimulus and reactions across multiple UVM agents. In the cited RISC-V vector processor verification environment, virtual sequences generate transactions for sub-interfaces, receive observed interface state through monitors and sequencers, and use UVM events to synchronize communication among dependent sub-interfaces.

Overview

A UVM virtual sequence is used in a UVM verification environment to coordinate stimulus across multiple interfaces or sub-interfaces. In the cited RISC-V Vector Processing Unit (VPU) verification setup, each virtual sequence creates interface-specific transactions that are sent to the corresponding interface agent.[1]

The environment described in the evidence used the Universal Verification Methodology (UVM) because it supports modular, scalable, and reusable verification environments.[2]

Role in a multi-interface UVM environment

In the VPU verification environment, the design exposed several semi-independent sub-interfaces. The verification team created one UVM agent per sub-interface. Each agent contained a sequencer, a driver, and a monitor connected to the relevant virtual interface.[3]

The virtual sequence sends transactions to the appropriate interface. The driver then stimulates the corresponding sub-interface using the values from the incoming transaction.[4]

Because the virtual sequence does not directly know when a transaction has been driven, the environment includes a monitor that captures the interface state and sends that information back to the virtual sequence through the sequencer. The virtual sequence can then react to the observed transaction and produce new stimulus.[5]

Synchronization and inter-sequence communication

The cited VPU environment had seven unique sub-interfaces that communicated with each other. To keep the sub-interfaces synchronized, the verification environment used UVM events, including their ability to transmit data along with an event trigger. This mechanism helped virtual sequences communicate with one another.[6]

Example: RISC-V Vector Processing Unit verification

In the VPU verification flow, constrained-random stimulus generation was complicated by dependencies among sub-interfaces. The team therefore randomized only the instructions sent to the issue sub-interface, while the other sub-interfaces reacted according to the driven instructions.[7]

After an instruction was supplied through the issue agent, the UVM environment followed the VPU instruction execution flow. The evidence identifies two observed or stimulated interfaces in this flow: DISPATCH, where the environment confirms or discards instruction execution in instruction order, and COMPLETED, where a monitor observes completion of a confirmed instruction and creates a transaction.[8]

Key characteristics from the cited use case

  • Creates interface-specific transactions for corresponding interfaces.
  • Works with UVM agents composed of sequencers, drivers, and monitors.
  • Receives observed interface state through monitor-to-sequencer feedback.
  • Reacts to observed transactions by producing additional stimulus.
  • Uses UVM events for synchronization and communication when multiple dependent sub-interfaces are present.

LINKED ENTITIES

1 links
Functional Verification of a RISC-V Vector Accelerator USES

CITATIONS

8 sources
8 citations
[1] The cited verification environment used UVM because it supports modular, scalable, and reusable verification environments. different
[2] Each virtual sequence creates interface-specific transactions that are sent to the corresponding interface. different
[3] The VPU verification environment created one agent for each sub-interface, and each agent contained a sequencer, a driver, and a monitor connected to the virtual interface. different
[4] When a driver receives a transaction, it stimulates the corresponding sub-interface using the incoming transaction values. different
[5] Because the virtual sequence does not know when a transaction is driven, a monitor captures interface state and sends it back to the virtual sequence through the sequencer; the virtual sequence then reacts and can produce new stimulus. different
[6] The environment used UVM events to synchronize seven communicating sub-interfaces and to ease virtual-sequence intercommunication. different
[7] Due to dependency among sub-interfaces, the VPU verification randomized only instructions fed to the issue sub-interface, while other sub-interfaces reacted according to the driven instructions. different
[8] After an instruction was fed through the issue agent, the UVM flow observed or stimulated DISPATCH and COMPLETED interfaces as part of instruction execution tracking. different