Skip to content
STIMSMITH

UVM Sequences

Concept WIKI v1 · 5/27/2026

UVM sequences are reusable, object-oriented stimulus-generation objects used in Universal Verification Methodology testbenches. They encapsulate stimulus logic, produce or coordinate sequence items through the sequencer-driver path, and can be specialized or replaced to vary verification behavior without restructuring the testbench.

Overview

UVM sequences are objects used in Universal Verification Methodology (UVM) testbenches to generate verification stimulus. In the provided UVM background material, sequences are described as an object-oriented approach to stimulus generation that encapsulates stimulus-generation logic into reusable objects, enabling efficient creation and modification of complex stimulus patterns. [C1]

UVM itself provides a SystemVerilog class framework for building verification testbenches, including components such as drivers, monitors, stimulus generators, and scoreboards. Within that framework, dynamic data objects called sequence items flow through the testbench. [C2]

Role in a UVM testbench

Sequences sit in the stimulus-generation path of a UVM environment. The cited material illustrates a sequence-to-sequencer-to-driver interaction in which a sequence item is passed through a UVM sequencer toward a UVM driver. [C3] This aligns with the broader UVM transaction-level modeling view: transactions are abstract representations of data transfers between components, allowing verification engineers to focus on functional behavior rather than direct signal or wire manipulation. [C4]

Because sequences are reusable objects, they are useful for building and modifying intricate stimulus patterns without rewriting the entire testbench. The cited source explicitly connects this encapsulation to improved verification productivity and efficiency. [C1]

Relationship to factory-based variation

The UVM factory supports replacing an object with a derived-type object without modifying the testbench structure or code. The source notes that this override capability is useful for altering sequence behavior as well as for exchanging one component version with another. [C5] In practice, this makes sequences a natural unit for test variation: a testbench can keep its overall structure while substituting a different sequence implementation when compatible with the expected interfaces and object types.

Example: Ibex UVM verification

The Ibex RISC-V core verification environment provides an example of how sequences are used in a production-style UVM testbench. The Ibex testbench runs binaries generated from RISC-DV and cross-checks execution against the Spike instruction-set simulator; additional stimulus includes randomized memory timings, memory errors, interrupts, and debug requests. [C6]

Within that environment, two memory interface agents are instantiated: one for the instruction-fetch interface and one for the load-store-unit interface. These agents run slave sequences that wait for memory requests from the core and then grant instruction or data requests. [C7]

The Ibex test and sequence library separates broad test coordination from focused stimulus. Tests coordinate activities such as loading the compiled assembly binary into the memory model, checking core status, and handling timeouts, while sequences are used to drive interrupt and debug stimulus into the core. [C8]

Automated sequence generation research

Recent research has explored automating UVM sequence generation with large language models while avoiding direct HDL generation. HAVEN, described in the public context, introduces a protocol-aware sequence domain-specific language that decomposes sequences into fine-grained step types. It first uses predefined DSL patterns to establish high-coverage sequences without LLM involvement, then iteratively uses LLM agents to analyze coverage-gap reports and compose additional targeted DSL sequences. [C9]

The same source reports that HAVEN uses a rule-based code generator for UVM sequences and evaluates the approach on 19 open-source IP designs across Direct, Wishbone, and AXI4-Lite protocols, reporting 100% compilation success, 90.6% average code coverage, and 87.9% average functional coverage. [C9]

Key takeaways

  • UVM sequences encapsulate stimulus-generation behavior as reusable objects. [C1]
  • Sequence items are the dynamic data objects that flow through UVM testbenches. [C2]
  • The sequence/sequencer/driver path is a core interaction pattern for driving stimulus. [C3]
  • Factory overrides can be used to alter sequence behavior without changing the surrounding testbench structure. [C5]
  • In real UVM environments such as Ibex verification, sequences can implement slave memory responses and targeted interrupt/debug stimulus. [C7][C8]

LINKED ENTITIES

1 links
UVM Factory supports_sequence_variation

CITATIONS

9 sources
9 citations
[1] C1: UVM sequences are object-oriented, reusable stimulus-generation objects that encapsulate stimulus logic and help create or modify complex stimulus patterns. [PDF] UVM based design verification of a RISC-V CPU core - POLITesi
[2] C2: UVM provides a SystemVerilog class framework for testbenches, and sequence items are dynamic data objects that flow through the testbench. [PDF] UVM based design verification of a RISC-V CPU core - POLITesi
[3] C3: UVM sequence items move through a sequence, UVM sequencer, and UVM driver interaction path. [PDF] UVM based design verification of a RISC-V CPU core - POLITesi
[4] C4: UVM transaction-level modeling represents data transfers as abstract transactions between components, helping engineers focus on functional behavior instead of low-level signal manipulation. [PDF] UVM based design verification of a RISC-V CPU core - POLITesi
[5] C5: The UVM factory can substitute derived-type objects without modifying testbench structure and is useful for altering sequence behavior. [PDF] UVM based design verification of a RISC-V CPU core - POLITesi
[6] C6: The Ibex UVM verification environment uses co-simulation against Spike, runs binaries produced by RISC-DV, and adds randomized memory timings, memory errors, interrupts, and debug requests. [PDF] UVM based design verification of a RISC-V CPU core - POLITesi
[7] C7: Ibex memory interface agents run slave sequences that wait for memory requests from the core and then grant instruction or data requests. [PDF] UVM based design verification of a RISC-V CPU core - POLITesi
[8] C8: In the Ibex test and sequence library, tests coordinate the overall flow while sequences drive interrupt and debug stimulus into the core. [PDF] UVM based design verification of a RISC-V CPU core - POLITesi
[9] C9: HAVEN uses a protocol-aware sequence DSL and rule-based generator for UVM sequence generation, with predefined DSL patterns and LLM-guided coverage-gap targeting; reported results include 100% compilation success, 90.6% average code coverage, and 87.9% average functional coverage on 19 open-source IP designs. HAVEN: Hybrid Automated Verification ENgine for UVM Testbench Synthesis with LLMs