Overview
Unordered floating-point reductions are discussed in the context of the RISC-V Vector Extension (RVV) as operations for which the RVV specification allows implementation-dependent behavior related to the reduction algorithm and rounding mode. Because floating-point addition is sensitive to operation ordering and rounding, a hardware implementation and a simulator can produce different results while still being considered correct under the allowed behavior described in the evidence.
Verification challenge
In a verification flow using Spike as a reference model for an RVV vector processing unit (VPU), unordered floating-point reductions caused occasional result mismatches. The reported issue was not necessarily a hardware error: mismatches could occur when the VPU result was correct according to the rounding mode and the reduction algorithm used.
The evidence describes two practical problems:
- False-positive mismatches: Spike and the VPU could disagree even when the VPU behavior was valid for the allowed reduction behavior.
- State divergence after a false positive: Even if the mismatch was identified as acceptable, the differing result remained in Spike's vector registers. Later vector instructions could consume that stale value and create additional mismatches unrelated to the original instruction.
Reference-model handling
To handle these cases, the verification flow added special support for unordered floating-point reductions. Instead of comparing the VPU result against Spike for these operations, the authors created an independent C reference model that implemented the same exact reduction algorithm as the device under test (DUT). The VPU result was then compared against this reduction-specific reference model.
If the VPU result matched the independent reduction model, the value was injected into Spike's vector register state. This avoided continuing execution with a divergent Spike state and reduced later false mismatches.
Relationship to RVV
The evidence explicitly frames unordered floating-point reductions as behavior allowed by the RVV specification and describes the work as part of accommodating Spike to the RISC-V vector specification version 0.7.1.