Definition
In the cited model-based testing setting, unit testing is a scenario where the test specification is described by pre-conditions and post-conditions on the inputs and results produced by the system under test (SUT). This scenario assumes control over the initial state and access to the internal states of the SUT after the test. [C1]
Relationship to sequence testing
The evidence describes unit testing as a special case of sequence testing: a unit test can be seen as a one-step sequence test where the output state is more or less completely accessible to the test. [C2]
Model-based unit testing pattern
For unit instruction testing in the VAMP processor conformance case study, the evidence gives a general test specification of the form:
test_spec pre σ ι ⟹ SUT σ ι =k exec_instr σ ι
Here, the SUT is compared against exec_instr, the model-level execution of an instruction. The relation =k is an executable conformance equality that compares register contents and the top k memory cells rather than infinite memory. [C3]
Test case structure
In the cited case study, each unit test case is composed of:
- an instruction,
- an initial configuration, and
- the resulting configuration after execution of the instruction. [C4]
HOL-TestGen can generate tests for all possible instructions from the specification. Subsets of instructions are isolated by adding a pre-condition that specifies the type of instruction under test. [C5]
Use in the VAMP case study
In the VAMP processor conformance study, unit testing is used to test each operation or instruction individually with different data. Sequence testing is used separately to test instruction sequences up to a given length. The study considers related instruction subsets, including memory-related load/store operations, arithmetic operations, logic operations, and control-flow-related operations. [C6]
Test purposes and pre-conditions
The evidence also identifies pre-conditions in test specifications as test purposes. These test purposes restrict generated test sequences or instruction sets to a desired subset; for example, a predicate such as is_load_store restricts a scenario to load and store operations. [C7]