Transaction Level Modeling Wiki

Overview

Transaction Level Modeling (TLM) is identified in the evidence as part of a SystemC-based modeling approach for building designs at different levels of abstraction. The cited processor-verification work states that its co-simulation testbench is implemented in SystemC and uses TLM. In that context, communication may be implemented either through signals, commonly used for RTL models, or through TLM transactions, commonly used for high-level algorithmic models.

Transaction structure

A TLM transaction object essentially contains:

a command, such as read or write;
the data payload to be transmitted; and
an address.

The evidence gives an example memory access operation using a TLM transaction object named gp, described as the tlm_generic_payload type. The memory obtains the address, access length, and data pointer from the transaction object, then executes either a data read or write depending on the TLM command.

Use in SystemC-based co-simulation

In the cited RISC-V processor-verification testbench, TLM is used together with SystemC. SystemC is described as a C++ class library with an event-driven simulation kernel, where design structure is described with modules and behavior is modeled in processes triggered by events.

The testbench co-simulates an RTL core under test and an instruction-set simulator reference model. Its memory interfaces translate back and forth between RTL core signals and TLM transactions. The work explicitly states that TLM transactions are leveraged to provide a unified memory abstraction for both the RTL core and the ISS based on a common standard.

Role in memory modeling

The cited co-simulation design uses separate instruction and data memory interfaces for the RTL core, and the ISS also uses two separate memory interfaces to match the RTL core. In the data-memory path, write accesses store data, while read accesses return existing data or generate new random data if the address has not been accessed before. TLM transactions are the abstraction used at the memory-interface boundary to connect these behaviors across modeling levels.

Relationship to co-simulation testbenches

A co-simulation testbench can use Transaction Level Modeling to connect signal-level RTL components with higher-level models through transaction-based memory interfaces. In the cited example, the test controller alternates between letting the RTL core execute one instruction and letting the ISS execute the same instruction, then compares execution states; TLM supports this setup by abstracting memory communication between the two sides.