Overview

Test Vector Post-Processing is described as the second step in a cross-level processor verification approach based on co-simulation and Coverage-Guided Fuzzing (CGF). In that flow, the first step is a CGF-based fuzzing loop that generates a set of test vectors, and the second step is post-processing, which reduces the generated set.

Purpose

The stated purpose of the post-processing step is to reduce the manual labor of verification engineers. It does this by clustering test vectors that trigger mismatches, so that vectors detecting the same bug are encapsulated together rather than reviewed as unrelated failures.

Role in the verification flow

In the described processor verification flow, a fuzzer generates test vectors that are used as instruction streams for co-simulation. The co-simulation combines an RTL core under test with a reference instruction set simulator (ISS). During execution, an execution controller checks whether processor behaviors are equal by comparing register values. If the register values are not equal, this indicates a mismatch that can be used by the post-processing stage.

Instrumentation requirement

For post-processing, the co-simulation is compiled with more extensive logging instrumentation. This instrumentation provides the additional feedback required by the post-processing component to cluster mismatch-triggering test vectors.

Relationship to processor verification

Test Vector Post-Processing is used in processor verification as part of a CGF-based cross-level verification approach. Its role is not to generate test vectors, but to reduce and organize the generated set after mismatches have been observed.