Overview

TCG Transformation is a stage in the OpenVADL QEMU-generation flow. In the presented pipeline, a VADL specification is processed into VIAM, then a TCG Transformation lowers that representation into a lowered VIAM form, followed by C-code generation for a QEMU frontend. The generated frontend emits QEMU Tiny Code Generator (TCG) operations for guest instructions. [1]

Role in QEMU generation

The QEMU-generation flow shown for OpenVADL consists of decoder generation and a transformation path from VIAM through TCG Transformation, Lowered VIAM, and C-Code Generation into a QEMU Frontend. The resulting frontend is used in a QEMU system that executes a guest program. [1]

This transformation relies on QEMU's use of dynamic binary translation and an architecture-agnostic intermediate representation, TCG. The slides describe QEMU as an open-source machine emulator that uses DBT, has a modular architecture, and employs the architecture-agnostic TCG IR, which simplifies support for new architectures. [1]

Input and output representation

The input to the transformation is VIAM, the VADL Intermediate Architecture Model. For example, the RISC-V RV64I ADDI instruction X(rd) := X(rs1) + immS is represented in VIAM with field accesses, register reads and writes, an add operation, and instruction start/end nodes. [1]

After TCG Transformation, the lowered VIAM form for the same instruction contains TCG-oriented operations and temporaries, including fields such as rs1, immS, and rd, register variables, a constant variable, a temporary, and operations such as tcg_add and tcg_mov. [1]

Generated code example

For RISC-V 64 ADDI, the generated QEMU translation function shown in the evidence creates TCG variables for the destination register, source register, temporary, and immediate constant, then emits TCG operations:

static bool trans_addi(DisasContext *ctx, arg_addi *a) {
  TCGv_i64 reg_x_rd_dest = dest_x(ctx, a->rd);
  TCGv_i64 reg_x_rs1 = get_x(ctx, a->rs1);
  TCGv_i64 tmp_n4_0 = tcg_temp_new_i64();
  TCGv_i64 const_immS_n3 = tcg_constant_i64(a->immS);

  tcg_gen_add_i64(tmp_n4_0, reg_x_rs1, const_immS_n3);
  tcg_gen_mov_i64(reg_x_rd_dest, tmp_n4_0);

  return true;
}

This example illustrates how an instruction semantics expression from VADL/VIAM is lowered into QEMU TCG helper calls. [1]

Status and future work

The presented conclusion states that OpenVADL enables automatic generation of QEMU frontends from VADL specifications, achieved by lowering VIAM to TCG operations. Future work listed for the QEMU generator includes TCG vector support for tensor instructions, user-mode simulation, floating-point instruction support, and a cycle-approximate simulator based on the instruction-set simulator. [1]