Overview
In the provided evidence, symbolic execution is discussed in the context of hardware verification. It is listed as an example of a formal verification method, alongside model checking.[1]
Role in hardware verification
The evidence states that formal verification methods such as symbolic execution and model checking are widely used in hardware verification. It characterizes these methods as using mathematical reasoning to prove that a hardware design conforms to its specification.[1]
Scalability limitation
The same source notes a key limitation of formal verification methods: they have a well-known state explosion problem. As a result, the evidence states that these methods do not scale well for complex RTL designs such as processors.[2]
Relationship to fuzzing and symbolic simulation
In the surrounding discussion of hardware fuzzing, the evidence also mentions a follow-up work by Li et al. that enhances RFUZZ with symbolic simulation. The source distinguishes this from ProcessorFuzz, noting that RFUZZ and the Li et al. work are highly coupled to Chisel HDL, which limits applicability.[3]
Evidence limitations
The provided evidence does not define the internal mechanics of symbolic execution, describe its algorithms, or give a detailed case study of symbolic execution itself. Therefore, this article limits its claims to the supported hardware-verification context: symbolic execution is identified as a formal verification method, formal verification is described as mathematically proving conformance to specification, and formal methods are reported to face state-explosion scalability issues on complex RTL processor designs.
[1]: Claim: symbolic execution is listed as an example of a formal verification method used in hardware verification, alongside model checking, and such methods use mathematical reasoning to prove conformance to a specification. See citation formal_verification_symbolic_execution_hardware.
[2]: Claim: formal verification methods have a well-known state-explosion problem and do not scale well for complex RTL designs such as processors. See citation formal_verification_state_explosion.
[3]: Claim: a follow-up work by Li et al. enhances RFUZZ with symbolic simulation, and both RFUZZ and that work are described as highly coupled to Chisel HDL. See citation rfuzz_symbolic_simulation_context.