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STIMSMITH

Stimulus Coverage

Concept WIKI v1 · 5/25/2026

Stimulus Coverage (SC) is a verification metric used to measure how thoroughly generated stimulus exercises ISA features and system behaviours. In RISC-V verification flows, automatically generated coverage models, including those produced by ImperasFC/ImperasSC, help expose coverage gaps and support coverage closure.

Definition

Stimulus Coverage (SC) is a coverage metric that measures how thoroughly verification stimulus has exercised ISA features and system behaviours. It is described alongside Functional Coverage (FC) as a way to assess the completeness of stimulus with respect to relevant architectural and system-level behaviours.

Role in RISC-V verification

In RISC-V verification, Stimulus Coverage helps teams understand whether generated tests have exercised the intended instruction-set features and system behaviours. This makes it useful during coverage closure, the process of achieving sufficient functional and code coverage to provide confidence that relevant design behaviours have been tested.

Automated coverage models

The provided evidence identifies ImperasFC / ImperasSC as tools that auto-generate SystemVerilog coverage models for RISC-V ISA features. These tools provide detailed metrics and can expose coverage gaps. The same evidence states that automatically generated coverage models, for example through ImperasFC/SC, provide detailed insight into coverage gaps.

Related concepts

  • Functional Coverage (FC): Listed together with Stimulus Coverage as a metric for determining how thoroughly stimulus has exercised ISA features and system behaviours.
  • Coverage Closure: Stimulus Coverage contributes evidence toward coverage closure by identifying what has and has not been exercised by tests.
  • ImperasSC: A tool associated with automatically generated SystemVerilog coverage models and detailed coverage metrics for RISC-V ISA features.

CITATIONS

4 sources
4 citations
[1] Stimulus Coverage is a metric that measures how thoroughly stimulus exercises ISA features and system behaviours. source
[2] Automatically generated coverage models such as those from ImperasFC/SC provide insight into coverage gaps. source
[3] ImperasFC/ImperasSC auto-generate SystemVerilog coverage models for RISC-V ISA features and provide detailed metrics. source
[4] Coverage closure is the process of achieving sufficient functional and code coverage to provide confidence that relevant design behaviours have been tested. source