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riscv-arch-tests

CodeArtifact WIKI v1 · 6/25/2026

riscv-arch-tests is a self-checking RISC-V architectural compliance test suite, hosted on GitHub as tenstorrent/riscv_arch_tests, used by hardware verification flows to validate that implementations correctly support ISA features such as opcodes, extensions (including F, D, and C), and control-and-status register (CSR) interactions.

Overview

riscv-arch-tests is an Assembly-language, self-checking directed-test suite for the RISC-V Instruction Set Architecture. It is publicly available as the GitHub repository tenstorrent/riscv_arch_tests, which the public metadata describes as "Self checking RISC-V directed tests" (e8c8a109-6fbe-4965-932d-6dd8a9020ec5; https://github.com/tenstorrent/riscv_arch_tests).

Role in verification flows

In multi-level RISC-V processor verification methodologies, riscv-arch-tests is used together with riscv-tests as a standard compliance test suite executed inside an automated Continuous Integration pipeline. The compliance suites serve as "established benchmarks for verifying that the Instruction" set is implemented correctly, before the methodology proceeds to directed, benchmarking, and constrained-random test phases (e8c8a109-6fbe-4965-932d-6dd8a9020ec5).

What it validates

When integrated into a verification strategy, riscv-arch-tests is intended to provide exhaustive validation of ISA features, covering:

  • Various opcodes,
  • Extensions such as F, D, and C, and
  • Proper interactions with system registers (CSRs)

This is reported as ensuring that "every aspect of the design is rigorously validated, from basic compliance to resilience under real-world conditions" (e8c8a109-6fbe-4965-932d-6dd8a9020ec5).

Relationship to directed testing

Because the suite consists of hand-written, self-checking tests that target specific architectural behavior, it implements the directed-testing technique. It is typically run first in a layered methodology, prior to real-world benchmarks and constrained-random generation tools such as RISCV-DV (e8c8a109-6fbe-4965-932d-6dd8a9020ec5).

Repository characteristics

Public metadata for the repository at the time of capture indicates:

These figures are taken from the GitHub metadata accompanying the public context and are useful for orienting readers to the activity level of the project, but they are not claims about the technical content of the suite itself.

LINKED ENTITIES

1 links
Directed Testing IMPLEMENTS

CITATIONS

4 sources
4 citations
[1] riscv-arch-tests is a self-checking RISC-V directed test suite, hosted at tenstorrent/riscv_arch_tests. tenstorrent/riscv_arch_tests
[2] riscv-arch-tests is used alongside riscv-tests as a standard compliance test suite executed from an automated Jenkins Continuous Integration pipeline in multi-level RISC-V processor verification flows. Comprehensive lockstep verification for NaxRiscv SoC integrating ... and superscalar core supporting multiple ISA extensions (including RV32/64IMAFDC)
[3] riscv-arch-tests validates ISA features including various opcodes, extensions (F, D, C), and proper interactions with system registers (CSRs). Comprehensive lockstep verification for NaxRiscv SoC integrating ... and superscalar core supporting multiple ISA extensions (including RV32/64IMAFDC)
[4] The repository's primary language is Assembly and the project had 124 stars, 17 forks, with a last-updated timestamp of 2026-06-11. tenstorrent/riscv_arch_tests