riscv-arch-tests

CodeArtifact

riscv-arch-tests is a self-checking RISC-V architectural compliance test suite, hosted on GitHub as tenstorrent/riscv_arch_tests, used by hardware verification flows to validate that implementations correctly support ISA features such as opcodes, extensions (including F, D, and C), and control-and-status register (CSR) interactions.

First seen 6/25/2026

Last seen 6/25/2026

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Overview

riscv-arch-tests is an Assembly-language, self-checking directed-test suite for the RISC-V Instruction Set Architecture. It is publicly available as the GitHub repository tenstorrent/riscv_arch_tests, which the public metadata describes as "Self checking RISC-V directed tests" (e8c8a109-6fbe-4965-932d-6dd8a9020ec5; https://github.com/tenstorrent/riscv_arch_tests).

Role in verification flows

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Directed Testing implements → 70% 1e

The methodology executes riscv-arch-tests in the directed testing stage to check ISA conformance.

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CITATIONS

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4 citations — click to collapse

[1] riscv-arch-tests is a self-checking RISC-V directed test suite, hosted at tenstorrent/riscv_arch_tests. tenstorrent/riscv_arch_tests

[2] riscv-arch-tests is used alongside riscv-tests as a standard compliance test suite executed from an automated Jenkins Continuous Integration pipeline in multi-level RISC-V processor verification flows. Comprehensive lockstep verification for NaxRiscv SoC integrating ... and superscalar core supporting multiple ISA extensions (including RV32/64IMAFDC)

[3] riscv-arch-tests validates ISA features including various opcodes, extensions (F, D, C), and proper interactions with system registers (CSRs). Comprehensive lockstep verification for NaxRiscv SoC integrating ... and superscalar core supporting multiple ISA extensions (including RV32/64IMAFDC)

[4] The repository's primary language is Assembly and the project had 124 stars, 17 forks, with a last-updated timestamp of 2026-06-11. tenstorrent/riscv_arch_tests