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RISC vs CISC

Concept WIKI v1 · 5/27/2026

RISC and CISC are two broad families of instruction set architecture design. RISC emphasizes simple, single-purpose instructions and load-store style memory access, while CISC uses more complex instructions that can combine multiple lower-level operations such as memory access, computation, and storage.

Overview

RISC (reduced instruction set architecture) and CISC (complex instruction set architecture) are two broad macro-families used to classify many commercial instruction set architectures (ISAs). The distinction emerged with the development of the RISC concept in the late 1970s; over time, architectures that did not follow the RISC approach were often grouped under the umbrella term CISC. [C1]

An instruction set architecture defines the software-visible behavior of a processor: supported instructions, data types, registers, memory-management features such as addressing modes and virtual memory, and privilege levels. Different microarchitectures can implement the same ISA while still running the same machine code and producing the same architectural results. [C2]

RISC approach

The foundational RISC idea is that each instruction should perform a single specific function. RISC architectures focus on commonly used instructions, reducing instruction complexity and aiming to improve speed and processor efficiency. Less frequent operations are handled through separate routines rather than being encoded as complex single instructions. [C1]

RISC machines are generally described as having more registers and a simpler load-store memory access mechanism. A consequence is that operations that might be expressed as one complex instruction on a CISC machine may require multiple simpler instructions on a RISC machine. [C3]

CISC approach

CISC architectures use instructions that may encompass multiple lower-level tasks in one instruction. For example, a single CISC instruction can combine loading data from memory, performing a calculation, and storing the result back to memory. CISC instructions may also support multiple steps or a variety of addressing methods within a single instruction. [C1]

Compared with RISC machines, CISC machines are generally described as having fewer registers and performing memory accesses more frequently as part of their operations. [C3]

Code size and memory trade-off

A noted drawback of RISC design is that programs may require more memory space because an operation can expand into more instructions than in a CISC design. In the late 1970s, when memory was expensive, minimizing program memory size was important, and complex instruction sets helped address that constraint. The evidence notes that 1 MB of memory cost about $5,000 in the late 1970s, while by 1994 it was available for under $6, making the additional memory demands of RISC progressively less problematic. [C4]

The evidence illustrates this with a generic multiplication example: a CISC-style MUL 0A,1F instruction is contrasted with a RISC-style sequence of separate LOAD, MUL, and STOR instructions. [C5]

RISC-V as a modern RISC example

RISC-V is presented as a contemporary RISC ISA with a modular design made of alternative base parts and optional extensions. Its base ISA and extensions define instructions and encodings, control flow, registers, memory and addressing, logic/integer manipulation, and related architectural features. Standard extensions are specified to work with standard bases and with each other without conflict. [C6]

The RISC-V project began at the University of California, Berkeley in 2010, its first specifications were made public in 2011, and RISC-V International was formed in 2015 to support standardization and adoption. Unlike most other ISA designs, RISC-V is described as being provided under royalty-free open-source licenses. [C7]

Practical interpretation

The RISC/CISC distinction is best understood as an ISA-level design philosophy rather than a complete description of processor implementation. The same ISA can be implemented by different microarchitectures, and those implementations may differ internally while remaining binary-compatible at the ISA level. [C2]

LINKED ENTITIES

2 links
Instruction Set Architecture context_for
microarchitecture contrasted_with

CITATIONS

7 sources
7 citations
[1] RISC and CISC are broad ISA macro-families; the distinction began with the RISC concept in the late 1970s, and CISC became an umbrella term for architectures outside the RISC approach. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi
[2] An ISA defines software-visible CPU features and behavior, while microarchitecture refers to implementation techniques; different implementations of the same ISA can run the same executables. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi
[3] RISC generally uses more registers and simpler load-store memory access, while CISC generally has fewer registers and accesses memory frequently during operations. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi
[4] RISC programs may require more memory due to increased instruction counts; falling memory prices made this drawback less significant over time. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi
[5] A generic CISC multiplication instruction can be contrasted with a RISC sequence using separate load, multiply, and store instructions. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi
[6] RISC-V has a modular design with base parts and optional extensions; standard extensions are specified to work with standard bases and each other without conflict. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi
[7] RISC-V originated at UC Berkeley in 2010, published first specifications in 2011, and is described as royalty-free and open-source; RISC-V International was formed in 2015. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi