RISC vs CISC

Concept

RISC and CISC are two broad families of instruction set architecture design. RISC emphasizes simple, single-purpose instructions and load-store style memory access, while CISC uses more complex instructions that can combine multiple lower-level operations such as memory access, computation, and storage.

First seen 5/27/2026

Last seen 5/28/2026

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Overview

RISC (reduced instruction set architecture) and CISC (complex instruction set architecture) are two broad macro-families used to classify many commercial instruction set architectures (ISAs). The distinction emerged with the development of the RISC concept in the late 1970s; over time, architectures that did not follow the RISC approach were often grouped under the umbrella term CISC. [C1]

An instruction set architecture defines the software-visible behavior of a processor: supported instructions, data types, registers, memory-management features such as addressing modes and virtual memory, and privilege levels. Different microarchitectures can implement the same ISA while still running the same machine code and producing the same architectural results. [C2]

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Instruction Set Architecture context_for RISC and CISC are presented as macro-families of ISAs, and the evidence defines what an ISA specifies.

microarchitecture contrasted_with The evidence distinguishes ISA behavior from the microarchitecture techniques used to implement an ISA.

CITATIONS

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[1] RISC and CISC are broad ISA macro-families; the distinction began with the RISC concept in the late 1970s, and CISC became an umbrella term for architectures outside the RISC approach. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi

[2] An ISA defines software-visible CPU features and behavior, while microarchitecture refers to implementation techniques; different implementations of the same ISA can run the same executables. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi

[3] RISC generally uses more registers and simpler load-store memory access, while CISC generally has fewer registers and accesses memory frequently during operations. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi

[4] RISC programs may require more memory due to increased instruction counts; falling memory prices made this drawback less significant over time. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi

[5] A generic CISC multiplication instruction can be contrasted with a RISC sequence using separate load, multiply, and store instructions. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi

[6] RISC-V has a modular design with base parts and optional extensions; standard extensions are specified to work with standard bases and each other without conflict. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi

[7] RISC-V originated at UC Berkeley in 2010, published first specifications in 2011, and is described as royalty-free and open-source; RISC-V International was formed in 2015. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi