Overview
RISC-V ISA tests are verification binaries used for RISC-V processor verification. The cited MICRO-54 paper describes them as coming from a UC Berkeley GitHub repository containing unit tests that sweep through the base instructions defined in the RISC-V ISA. The same discussion characterizes these tests as checking basic functionality.
Role in processor verification
In the paper Effective Processor Verification with Logic Fuzzer Enhanced Co-simulation, RISC-V ISA tests are one of two sources of verification binaries used in the evaluation, alongside random instruction streams generated with Google's riscv-dv tool. The authors run these binaries in a co-simulation-based verification setup for RISC-V cores.
Evaluation usage in the MICRO-54 study
The MICRO-54 evaluation reports the following numbers of RISC-V ISA tests used per core:
| Core | Number of ISA tests | Number of random tests |
|---|---|---|
| CVA6 | 228 | 120 |
| BlackParrot | 215 | 150 |
| BOOM | 228 | 120 |
These tests are used as part of an evaluation methodology where the authors first run binaries on a base setup with Dromajo enabled, then rerun the same binaries with Logic Fuzzers enabled to expose additional bugs.
Limitations noted in the evidence
The paper groups RISC-V ISA tests with other general RISC-V verification resources and states that they only check basic functionality. It contrasts this with broader verification goals involving co-simulation and logic-fuzzer-enhanced execution, where additional stimuli can expose bugs beyond those found by the base test binaries alone.