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push_gpr_to_kernel_stack

CodeArtifact WIKI v1 · 5/26/2026

push_gpr_to_kernel_stack() is a RISC-V assembly-generation helper referenced in the riscv_asm_program_gen flow. Its documented role is to push general-purpose registers to the stack for trap handling.

push_gpr_to_kernel_stack

push_gpr_to_kernel_stack() is a code artifact referenced in the RISC-V assembly program generation flow described for riscv_asm_program_gen.[C1]

Purpose

The documented purpose of push_gpr_to_kernel_stack() is to push general-purpose registers to the stack for trap handling.[C1]

Generation-flow context

In the described flow, main-program and sub-program generation occur first. After that, host-interface-related instructions are added using gen_section(), including a write_tohost section and an _exit label.[C2]

push_gpr_to_kernel_stack() is then invoked or generated as part of the trap-handling setup. The same evidence states that riscv_asm_program uses gen_section() to select the mtvec_handler instruction section, which has exception_handler and interrupt_handler defined.[C3]

Role in generated RISC-V programs

The surrounding riscv_asm_program_gen machinery, together with instruction-sequence, base-test, and helper classes, generates complete RISC-V assembly programs with randomized instructions and randomized general-purpose register selections.[C4] Within that generated program context, push_gpr_to_kernel_stack() belongs to the trap-handling support path rather than the randomized instruction body itself.[C1]

LINKED ENTITIES

2 links
riscv_asm_program_gen generation_flow_context
gen_section sequenced_with

CITATIONS

4 sources
4 citations
[1] push_gpr_to_kernel_stack() pushes general-purpose registers to the stack for trap handling. RISC-V source class riscv_asm_program_gen, the brain behind ...
[2] After main and sub-program generation, host-interface-related instructions are added by gen_section(), including write_tohost and _exit content. RISC-V source class riscv_asm_program_gen, the brain behind ...
[3] riscv_asm_program uses gen_section() to select mtvec_handler, which has exception_handler and interrupt_handler defined. RISC-V source class riscv_asm_program_gen, the brain behind ...
[4] The surrounding generator flow produces complete RISC-V assembly programs with randomized instructions and randomized GPR selections. RISC-V source class riscv_asm_program_gen, the brain behind ...