Processor-UVM-Verification
CodeArtifactA GitHub-hosted code artifact providing a SystemVerilog and UVM-based verification environment for a 5-stage pipelined MIPS processor, authored by gupta409 with a contribution from rpjayaraman enabling live access on EDA Playground.
First seen 8/11/2026
Last seen 8/11/2026
Evidence 1 chunks
Wiki v1
WIKI
Processor-UVM-Verification
Overview
Processor-UVM-Verification is a public code repository hosted on GitHub under the user account gupta409. It implements a verification environment, written in SystemVerilog and built around the Universal Verification Methodology (UVM), for a 5-stage pipelined MIPS processor design-under-test (DUT).
NEIGHBORHOOD
No graph connections found for this entity yet. It may appear in future ingestion runs.
explore full graph →RELATIONSHIPS
4 connectionsThe repository implements SystemVerilog-based verification as its core methodology.
The project uses a UVM environment for verification.
The project can be accessed and run live on EDA Playground.
gupta409 owns the repository as indicated by the GitHub URL.
CITATIONS
4 sources4 citations — click to collapse
[1] The artifact performs SystemVerilog-based verification of a 5-stage pipelined MIPS processor using a UVM environment. gupta409/Processor-UVM-Verification
[2] A project report PDF is included in the repository under Documentation/Report.pdf. gupta409/Processor-UVM-Verification — Documentation/Report.pdf
[3] Contributor rpjayaraman enabled live access to the project on EDA Playground. EDA Playground live workspace for Processor-UVM-Verification
[4] The repository metadata reports 124 stars and 36 forks, with the last update on 2026-07-15. gupta409/Processor-UVM-Verification (GitHub repository metadata)