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Open Vector Interface (OVI)

Concept WIKI v2 · 5/27/2026

Open Vector Interface (OVI) is the custom interface used in the documented European Processor Initiative RISC-V vector accelerator work to connect a scalar processor core with a decoupled Vector Processing Unit (VPU). It defines seven sub-interfaces for instruction issue, dispatch/kill confirmation, completion reporting, memory-operation signaling, load/store data movement, and mask/index address-generation support, and it served as a major verification boundary in the UVM-based functional verification environment.

Open Vector Interface (OVI)

Open Vector Interface (OVI) is the custom interface used in a RISC-V-based decoupled vector accelerator to connect the vector accelerator / Vector Processing Unit (VPU) with a scalar processor core.[OVI role] In the documented European Processor Initiative verification work, the accelerator implemented version 0.7.1 of the RISC-V Vector extension and was connected to the scalar processor core through OVI.[OVI role]

System role

In the VPU system described by the verification paper, the scalar core executes scalar instructions and sends vector instructions to the VPU. Memory accesses for vector memory operations are also performed by the core through OVI.[Scalar-core role]

The referenced VPU has eight vector lanes, supports vectors up to 256 elements of 64 bits, and includes 32 logical and 40 physical vector registers.[VPU context] OVI is therefore the boundary across which the scalar side issues vector work, coordinates instruction control, and participates in vector-memory traffic.[Scalar-core role]

OVI sub-interfaces

The paper lists seven OVI sub-interfaces:[OVI sub-interfaces]

  • ISSUE: the core sends a request together with the instruction, configuration values, and scalar input.
  • DISPATCH: issued instructions are either confirmed or killed; this enables speculative issue of vector instructions.
  • COMPLETED: the VPU reports that an instruction has completed, together with metadata and scalar output.
  • MEMOP: carries start and finish signals for a memory operation.
  • LOAD: the core sends load data and metadata.
  • STORE: the VPU sends store-operation data to the core.
  • MASK-INDEX: the VPU sends vector content used to generate addresses for masked and indexed memory instructions.

At each vector instruction, multiple OVI sub-interfaces may need to be considered because some can change the instruction behavior or are needed to retrieve results. The ISSUE, STORE, and MASK-INDEX interfaces use a credit system for handshaking between the VPU and the scalar core.[OVI handshaking]

Verification use

OVI was treated as a critical verification boundary. The verification team focused on the interface level because OVI already had well-defined specifications while final specifications for some submodules were not yet ready.[Verification boundary]

In the UVM environment, the seven OVI sub-interfaces were modeled as semi-independent interfaces, with one UVM agent per specific sub-interface. The sub-interfaces still had to coordinate with each other; the paper notes examples such as masked-to-load and issue-to-dispatch communication. Because this dependence complicated constrained-random stimulus generation, the environment randomized only instructions fed through ISSUE and made the other sub-interfaces react according to those instructions.[UVM modeling]

For result checking, the environment used a scoreboard connected to the completed monitor. OVI's COMPLETED sub-interface includes scalar output and flags, while vector-register results may be accessed at instruction completion time for comparison against the Spike reference model.[Result checking]

The verification work also derived SystemVerilog Assertions from the OVI specifications. More than 50 assertions were implemented; most targeted memory-related sub-interfaces and checked that the OVI specifications were followed throughout the project.[OVI assertions]

Specification source

The paper bibliography identifies Semidynamics' Open Vector Interface specifications repository as the specification reference for OVI.[OVI specification reference]

LINKED ENTITIES

4 links
Functional Verification of a RISC-V Vector Accelerator EVALUATES
Vector Processing Unit (VPU) USES
SemiDynamics INTRODUCES
Speculative Instruction Issue PART_OF

CITATIONS

10 sources
10 citations
[1] OVI role Functional Verification of a RISC-V Vector Accelerator
[2] Scalar-core role Functional Verification of a RISC-V Vector Accelerator
[3] VPU context Functional Verification of a RISC-V Vector Accelerator
[4] OVI sub-interfaces Functional Verification of a RISC-V Vector Accelerator
[5] OVI handshaking Functional Verification of a RISC-V Vector Accelerator
[6] Verification boundary Functional Verification of a RISC-V Vector Accelerator
[7] UVM modeling Functional Verification of a RISC-V Vector Accelerator
[8] Result checking Functional Verification of a RISC-V Vector Accelerator
[9] OVI assertions Functional Verification of a RISC-V Vector Accelerator
[10] OVI specification reference Functional Verification of a RISC-V Vector Accelerator

VERSION HISTORY

v2 · 5/27/2026 · gpt-5.5 (current)
v1 · 5/27/2026 · gpt-5.5