Overview

Memory Operations Stimulus is the test-generation and verification-environment stimulus used to exercise vector memory operations in a RISC-V Vector Processing Unit (VPU) verification flow. The cited environment used RISCV-DV to generate random RISC-V assembly tests, including vector instructions, and modified its memory-operation generation so tests could change element width and vector length through generated vsetvli instructions. The flow also added selectable data-page initialization patterns and constrained test memory addresses to avoid memory exceptions, especially for vector indexed memory instructions.

Role in the verification environment

Memory operations were treated as a delicate part of the design because the VPU did not directly access memory. Instead, it read and wrote data through the scalar core using memop, load, store, and mask interfaces. These interfaces required significant communication between sub-interfaces, so the stimulus had to coordinate generated instructions, reference data, memory-model contents, masks, indexes, and completion behavior.

The environment used Spike in two relevant ways: as the scalar core that executed scalar instructions and provided vector instructions to the UVM environment in program order, and as a golden/reference model for comparing DUT results. Spike was also modified with functions to read from Spike memory and to resume simulation until a vector instruction was encountered, returning reference results and other instruction data to UVM.

Load-operation stimulus

For load operations, the verification environment needed the expected memory data before the instruction executed. Alongside instruction information from Spike, the environment obtained the data that should be read, wrote it into a UVM memory model based on the OpenTitan memory model, and then sent the Spike-provided data through the VPU load sub-interface at the corresponding addresses.

This ensured that generated load instructions were backed by known reference memory contents and could be checked against the VPU behavior.

Store-operation stimulus

For store operations, the environment needed memory contents before instruction execution so that masked stores could be checked and undesired writes could be detected. During a store, the VPU sent data that was stored in the memory model. Later, those memory-model values were read and compared with Spike values.

This store stimulus supported checking both correct writes and preservation of locations that should not have been modified.

Masked and indexed memory-operation stimulus

Masked memory operations produced outgoing transactions from the VPU containing masks or indexes. The environment needed these masks or indexes to execute the instruction on the verification side and compare the behavior with Spike. The cited work reports that this comparison helped identify the source of many mask-related memory-instruction errors.

The RISCV-DV changes also specifically constrained memory addresses accessed by generated tests to avoid memory exceptions, with special attention to vector memory indexed instructions.

Retry and vstart scenarios

The OVI-based environment included retry behavior for memory operations. Retries occurred when the VPU could not handle all loaded cache lines sent by the scalar core. In such cases, the instruction completed with a vstart value that identified the first element that could not be written to the vector registers; the instruction then had to be re-executed from that element after killing later instructions.

The verification flow randomized memory exceptions for multiple in-flight loads and stores, causing failing instructions to be killed, and added complexity in calculating the correct vstart value from the lowest received index, mask, or data chunk. Because retries were a major source of VPU errors, the environment used UVM configuration objects to randomize and increase the chance of retry scenarios. Directed tests with different vstart values were also added to regression testing for load retry coverage.

Relationship to RISCV-DV

RISCV-DV provided the random assembly-test generation used to stress the VPU. For memory-operation stimulus, it was extended to generate vsetvli instructions, modify memory-operation generation for varying vector length and element width, select data-page initialization patterns, constrain accessed memory addresses, and adapt to the RVV 0.7.1 specification.