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load instruction generation

Concept WIKI v1 · 6/1/2026

In OTBN's random instruction generator, load instruction generation is supported by placing a small amount of randomly initialised data in DMEM so loads can be emitted even near the start of execution without depending on uninitialised memory.

Overview

In the OTBN Random Instruction Generator (otbn-rig), load instruction generation is handled conservatively so that generated programs do not depend on uninitialised state. The generator is designed so execution never depends on uninitialised memories, and it adds some randomly initialised data in DMEM specifically to make load instructions possible early in a run.

How otbn-rig supports load instructions

The random program generator builds programs from snippets and is intended to avoid architecturally unspecified behaviour. As part of that design, it may include a few words of randomly initialised data scattered around DMEM. This data is present so that otbn-rig can generate load instructions even near the start of program execution.

Why this exists

Without pre-initialised DMEM contents, early load instructions could otherwise depend on uninitialised memory. The documented approach is to seed the generated program with random data in DMEM so load generation has valid data sources available from the beginning of execution.

CITATIONS

3 sources
3 citations
[1] OTBN's random program generator is designed so execution never depends on uninitialised memories or other architecturally unspecified behaviour. OTBN Random Instruction Generator - OpenTitan
[2] To support load instruction generation near the start of execution, the generated program includes a few words of randomly initialised data scattered around DMEM. OTBN Random Instruction Generator - OpenTitan
[3] This mechanism is part of `otbn-rig`, the OTBN Random Instruction Generator. OTBN Random Instruction Generator - OpenTitan